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ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 1 ? 2011?2016 xilinx, inc. xilinx, the xilinx logo, virtex, kintex, artix, zynq, spartan, ise, vivado and other designated brands included herein are trademarks of xilinx in the united states and other countries. all other tradema rks are the property of their respective owners. introduction virtex?-7 t and xt fpgas are available in -3, -2, -1, and -2l speed grades, with -3 having the highest performance. the -2l devices operate at v ccint = 1.0v and are screened for lower maximum stat ic power. the spee d specification of a -2l device is the same as the -2 speed grade. the -2g speed grade is available in de vices utilizing stacked silicon interconnect (ssi) technology. the -2g speed grade supports 12.5 gb/s gtx or 13.1 gb/s gth transceivers as well as the standard -2 speed grade specifications. virtex-7 t and xt fpga dc and ac characteristics are specified in commercial, exte nded, industrial, and military temperature ranges. except for the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1m speed grade military device are the same as for a -1c speed grade commercial device). however, only selected speed grades and/or devices are available in each temperature range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. available device and package combinations can be found in : ? 7 series fpgas overview ( ds180 ) ? defense-grade 7 series fpgas overview ( ds185 ) this virtex-7 t and xt fpga data sheet, part of an overall set of documentation on the 7 series fpgas, is available on the xilinx website at www.xilinx.com/7 . dc characteristics virtex-7 t and xt fp gas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 product specification table 1: absolute maximum ratings (1) symbol description min max units fpga logic v ccint internal supply voltage ?0.5 1.1 v v ccaux auxiliary supply voltage ?0.5 2.0 v v ccbram supply voltage for the block ram memories ?0.5 1.1 v v cco output drivers supply voltage for 3.3v hr i/o banks ?0.5 3.6 v output drivers supply voltage for 1.8v hp i/o banks ?0.5 2.0 v v ccaux_io auxiliary supply voltage ?0.5 2.06 v v ref input reference voltage ?0.5 2.0 v v in (2)(3)(4) i/o input voltage for 3.3v hr i/o banks ?0.40 v cco +0.55 v i/o input voltage for 1.8v hp i/o banks ?0.55 v cco +0.55 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (5) ?0.40 2.625 v v ccbatt key memory battery backup supply ?0.5 2.0 v gtx and gth transceivers v mgtavcc analog supply voltage for the gtx/gth tr ansmitter and receiver circuits ?0.5 1.1 v v mgtavtt analog supply voltage for the gtx/gth transmit ter and receiver termination circuits ?0.5 1.32 v v mgtvccaux auxiliary analog quad pll (qpll) voltage s upply for the gtx/gth transceivers ?0.5 1.935 v v mgtrefclk gtx/gth transceiver reference cl ock absolute input voltage ?0.5 1.32 v s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 2 v mgtavttrcal analog supply voltage for the resistor calib ration circuit of the gtx/gth transceiver column ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (txp/ txn) absolute input voltage ?0.5 1.26 v i dcin-float dc input current for receiver input pins dc coupled rx termination = floating ? 14 ma i dcin-mgtavtt dc input current for receiver input pins dc coupled rx termination = v mgtavtt ? 12 ma i dcin-gnd dc input current for receiver input pins dc coupled rx termination = gnd ? 6.5 ma i dcout-float dc output current for transmitter pins dc coupled rx termination = floating ? 14 ma i dcout-mgtavtt dc output current for transmitter pi ns dc coupled rx termination = v mgtavtt ? 12 ma xadc v ccadc xadc supply relative to gndadc ?0.5 2.0 v v refp xadc reference input relative to gndadc ?0.5 2.0 v temperature t stg storage temperature (ambient) ?65 150 c t sol maximum soldering temperature for pb/sn component bodies (6) ?+220c maximum soldering temperature for pb-free component bodies (6) ?+260c t j maximum junction temperature (6) ? +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other c onditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. the lower absolute voltage specification always applies. 3. for i/o operation, refer to the 7 series fpgas selectio resources user guide ( ug471 ). 4. the maximum limit applies to dc signals. for maximum undershoot and overshoot ac specifications, see table 4 and table 5 . 5. see table 10 for tmds_33 specifications. 6. for soldering guidelines and thermal considerations, see the 7 series fpga packaging and pinout specification ( ug475 ). table 2: recommended operating conditions (1)(2) symbol description min typ max units fpga logic v ccint (3) internal supply voltage 0.97 1.00 1.03 v internal supply voltage for -1c device s with voltage identification (vid) bit programmed to run at 0.9v typical (4) . 0.87 0.90 0.93 v v ccbram (3) block ram supply voltage 0.97 1.00 1.03 v block ram supply voltage for -1c devi ces with voltage identification (vid) bit programmed to run at 0.9v typical (4) . 0.87 0.90 1.03 v v ccaux auxiliary supply vo ltage 1.71 1.80 1.89 v v cco (5)(6) supply voltage for 3.3v hr i/o banks 1.14 ? 3.465 v supply voltage for 1.8v hp i/o banks 1.14 ? 1.89 v v ccaux_io (7) auxiliary supply voltage when set to 1.8v 1.71 1.80 1.89 v auxiliary supply voltage when set to 2.0v 1.94 2.00 2.06 v v in (8) i/o input voltage ?0.20 ? v cco +0.2 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (9) ?0.20 ? 2.625 v i in (10) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ??10ma table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 3 v ccbatt (11) battery voltage 1.0 ? 1.89 v gtx and gth transceivers v mgtavcc (12) analog supply voltage for the gtx/gth transceiver qpll frequency range 10.3125 ghz (13)(14) 0.97 1.0 1.08 v analog supply voltage for the gtx/gth transceiver qpll frequency range > 10.3125 ghz 1.02 1.05 1.08 v v mgtavtt (12) analog supply voltage for the gt x/gth transmitter and receiver termination circuits 1.17 1.2 1.23 v v mgtvccaux (12) auxiliary analog quad pll (qpll) voltage supply for the transceivers 1.75 1.80 1.85 v v mgtavttrcal (12) analog supply voltage for the resistor calibration circuit of the gtx/gth transceiver column 1.17 1.2 1.23 v xadc v ccadc xadc supply relative to gndadc 1.71 1.80 1.89 v v refp externally supplied reference voltage 1.20 1.25 1.30 v temperature t j junction temperature operating range for commercial (c) temperature devices 0?85c junction temperature operating r ange for extended (e) temperature devices 0 ? 100 c junction temperature operating range for i ndustrial (i) temperature devices ?40 ? 100 c junction temperature operating range fo r military (m) temperature devices ?55 ? 125 c notes: 1. all voltages are relative to ground. 2. for the design of the power distribution system, consult the 7 series fpgas pcb design and pin planning guide ( ug483 ). 3. v ccint and v ccbram should be connected to the same supply. 4. for more information on the vid bit see the lowering power using the voltage identification bit application note ( xapp555 ). 5. configuration data is retained even if v cco drops to 0v. 6. includes v cco of 1.2v, 1.35v, 1.5v, 1.8v, 2.5v ( hr i/o only), 3.3v (hr i/o only) at 5%. 7. for more informatio n, refer to the v ccaux_io section of 7 series fpgas selectio resources user guide ( ug471 ). 8. the lower absolute voltage specification always applies. 9. see table 10 for tmds_33 specifications. 10. a total of 200 ma per bank should not be exceeded. 11. v ccbatt is required only when using bitstream encryp tion. if battery is not used, connect v ccbatt to either ground or v ccaux . 12. each voltage listed requires the filter circuit described in the 7 series fpgas gtx/gth tr ansceiver user guide ( ug476 ). 13. for data rates 10.3125 gb/s, v mgtavcc should be 1.0v 3% for lower power consumption. 14. for lower power consumption, v mgtavcc should be 1.0v 3% over the entire cpll frequency range. table 3: dc characteristics over re commended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 ? ? v v dri data retention v ccaux voltage (below which configuration data might be lost) 1.5 ? ? v i ref v ref leakage current per pin ? ? 15 a i l input or output leakage current per pin (sample-tested) ? ? 15 a c in (2) die input capacitance at the pad ? ? 8 pf table 2: recommended operating conditions (1)(2) (cont?d) symbol description min typ max units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 4 i rpu pad pull-up (when selected) @ v in =0v, v cco = 3.3v 90 ? 330 a pad pull-up (when selected) @ v in =0v, v cco = 2.5v 68 ? 250 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 34 ? 220 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 23 ? 150 a pad pull-up (when selected) @ v in =0v, v cco = 1.2v 12 ? 120 a i rpd pad pull-down (when selected) @ v in = 3.3v 68 ? 330 a pad pull-down (when selected) @ v in = 1.8v 45 ? 180 a i ccadc analog supply current, analog circuits in powered up state ? ? 25 ma i batt (3) battery supply current ? ? 150 na r in_term (4) thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_40) 28 40 55 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_50) 35 50 65 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_60) 44 60 83 n temperature diode ideality factor ? 1.010 ? ? r temperature diode series resistance ? 2 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. this measurement represents the die capacitance at the pad, not including the package. 3. maximum value specified for worst case process at 25c. 4. termination resistance to a v cco /2 level. table 4: v in maximum allowed ac voltage overshoot and undershoot for 3.3v hr i/o banks (1)(2) ac voltage overshoot % of ui @?55c to 125c ac voltage undershoot % of ui @?55c to 125c v cco + 0.55 100 ?0.40 100 ?0.45 61.7 ?0.50 25.8 ?0.55 11.0 v cco + 0.60 46.6 ?0.60 4.77 v cco + 0.65 21.2 ?0.65 2.10 v cco + 0.70 9.75 ?0.70 0.94 v cco + 0.75 4.55 ?0.75 0.43 v cco + 0.80 2.15 ?0.80 0.20 v cco + 0.85 1.02 ?0.85 0.09 v cco + 0.90 0.49 ?0.90 0.04 v cco + 0.95 0.24 ?0.95 0.02 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ? 0.20v, must not exceed the values in this table. table 3: dc characteristics over re commended operating conditions (cont?d) symbol description min typ (1) max units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 5 table 5: v in maximum allowed ac voltage overshoot and undershoot for 1.8v hp i/o banks (1)(2) ac voltage overshoot % of ui @?55c to 125c ac voltage undershoot % of ui @?55c to 125c v cco + 0.55 100 ?0.55 100 v cco + 0.60 50.0 (3) ?0.60 50.0 (3) v cco + 0.65 50.0 (3) ?0.65 50.0 (3) v cco + 0.70 47.0 ?0.70 50.0 (3) v cco + 0.75 21.2 ?0.75 50.0 (3) v cco + 0.80 9.71 ?0.80 50.0 (3) v cco + 0.85 4.51 ?0.85 28.4 v cco + 0.90 2.12 ?0.90 12.7 v cco + 0.95 1.01 ?0.95 5.79 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ? 0.20v, must not exceed the values in this table. 3. for ui lasting less than 20 s. table 6: typical quiescent supply current symbol description device speed grade units -3 -2g -2 -2l -1 -1m i ccintq quiescent v ccint supply current xc7v585t 1483 1483 1483 1483 1483 n/a ma xc7v2000t n/a 3756 3756 3756 3756 n/a ma xc7vx330t 1012 1012 1012 1012 1012 n/a ma xc7vx415t 1324 1324 1324 1324 1324 n/a ma xc7vx485t 1578 1578 1578 1578 1578 n/a ma xc7vx550t 2214 2214 2214 2214 2214 n/a ma xc7vx690t 2214 2214 2214 2214 2214 n/a ma XC7VX980T n/a 2580 2580 2580 2580 n/a ma xc7vx1140t n/a 3448 3448 3448 3448 n/a ma xq7v585t n/a n/a 1483 1483 1483 1483 ma xq7vx330t n/a n/a 1012 1012 1012 1012 ma xq7vx485t n/a n/a 1578 1578 1578 1578 ma xq7vx690t n/a n/a 2214 n/a 2214 n/a ma xq7vx980t n/a n/a n/a 2580 2580 n/a ma s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 6 i ccoq quiescent v cco supply current xc7v585t 1 1 1 1 1 n/a ma xc7v2000t n/a 1 1 1 1 n/a ma xc7vx330t 1 1 1 1 1 n/a ma xc7vx415t 1 1 1 1 1 n/a ma xc7vx485t 1 1 1 1 1 n/a ma xc7vx550t 1 1 1 1 1 n/a ma xc7vx690t 1 1 1 1 1 n/a ma XC7VX980T n/a 1 1 1 1 n/a ma xc7vx1140t n/a 1 1 1 1 n/a ma xq7v585t n/a n/a 1 1 1 1 ma xq7vx330t n/a n/a 1 1 1 1 ma xq7vx485t n/a n/a 1 1 1 1 ma xq7vx690t n/a n/a 1 n/a 1 n/a ma xq7vx980t n/a n/a n/a 1 1 n/a ma i ccauxq quiescent v ccaux supply current xc7v585t 114 114 114 114 114 n/a ma xc7v2000t n/a 315 315 315 315 n/a ma xc7vx330t 73 73 73 73 73 n/a ma xc7vx415t 88 88 88 88 88 n/a ma xc7vx485t 104 104 104 104 104 n/a ma xc7vx550t 147 147 147 147 147 n/a ma xc7vx690t 147 147 147 147 147 n/a ma XC7VX980T n/a 183 183 183 183 n/a ma xc7vx1140t n/a 250 250 250 250 n/a ma xq7v585t n/a n/a 114 114 114 114 ma xq7vx330t n/a n/a 73 73 73 73 ma xq7vx485t n/a n/a 104 104 104 104 ma xq7vx690t n/a n/a 147 n/a 147 n/a ma xq7vx980t n/a n/a n/a 183 183 n/a ma table 6: typical quiescent supply current (cont?d) symbol description device speed grade units -3 -2g -2 -2l -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 7 i ccaux_ioq quiescent v ccaux_io supply current xc7v585t 2 2 2 2 2 n/a ma xc7v2000t n/a 2 2 2 2 n/a ma xc7vx330t 2 2 2 2 2 n/a ma xc7vx415t 2 2 2 2 2 n/a ma xc7vx485t 2 2 2 2 2 n/a ma xc7vx550t 2 2 2 2 2 n/a ma xc7vx690t 2 2 2 2 2 n/a ma XC7VX980T n/a 2 2 2 2 n/a ma xc7vx1140t n/a 2 2 2 2 n/a ma xq7v585t n/a n/a 2 2 2 2 ma xq7vx330t n/a n/a 2 2 2 2 ma xq7vx485t n/a n/a 2 2 2 2 ma xq7vx690t n/a n/a 2 n/a 2 n/a ma xq7vx980t n/a n/a n/a 2 2 n/a ma i ccbramq quiescent v ccbram supply current xc7v585t 34 34 34 34 34 n/a ma xc7v2000t n/a 56 56 56 56 n/a ma xc7vx330t 32 32 32 32 32 n/a ma xc7vx415t 38 38 38 38 38 n/a ma xc7vx485t 44 44 44 44 44 n/a ma xc7vx550t 63 63 63 63 63 n/a ma xc7vx690t 63 63 63 63 63 n/a ma XC7VX980T n/a 65 65 65 65 n/a ma xc7vx1140t n/a 81 81 81 81 n/a ma xq7v585t n/a n/a 34 34 34 34 ma xq7vx330t n/a n/a 32 32 32 32 ma xq7vx485t n/a n/a 44 44 44 44 ma xq7vx690t n/a n/a 63 n/a 63 n/a ma xq7vx980t n/a n/a n/a 65 65 n/a ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (t j ) with single-ended selectio resources. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. use the xilinx power estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to estimate static power consumption for conditions other than those specified. table 6: typical quiescent supply current (cont?d) symbol description device speed grade units -3 -2g -2 -2l -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 8 power-on/off power supply sequencing the recommended power-on sequence is v ccint , v ccbram , v ccaux , v ccaux_io , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off sequence is the reverse of the power- on sequence. if v ccint and v ccbram have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. if v ccaux , v ccaux_io , and v cco have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. for v cco voltages of 3.3v in hr i/o banks and configuration bank 0: ? the voltage difference between v cco and v ccaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cy cle to maintain device reliability levels. ?the t vcco2vccaux time can be allocated in any percentage between the power-on and power-off ramps. the recommended power-on sequence to achieve minimum current draw for the gtx/gth transceivers is v ccint , v mgtavcc , v mgtavtt or v mgtavcc , v ccint , v mgtavtt . there is no recommended sequencing for v mgtvccaux . both v mgtavcc and v ccint can be ramped simultaneously. the recommended power-off sequence is the reverse of the power- on sequence to achieve minimum current draw. if these recommended sequences are not met, current drawn from v mgtavtt can be higher than specifications during power-up and power-down. ? when v mgtavtt is powered before v mgtavcc and v mgtavtt ?v mgtavcc > 150 mv and v mgtavcc < 0.7v, the v mgtavtt current draw can increase by 460 ma per transceiver during v mgtavcc ramp up. the duration of the current draw can be up to 0.3 x t mgtavcc (ramp time from gnd to 90% of v mgtavcc ). the reverse is true for power-down. ? when v mgtavtt is powered before v ccint and v mgtavtt ?v ccint > 150 mv and v ccint <0.7v, the v mgtavtt current draw can increase by 50 ma per transceiver during v ccint ramp up. the duration of the current draw can be up to 0.3 x t vccint (ramp time from gnd to 90% of v ccint ). the reverse is true for power-down. there is no recommended sequence for supplies not shown. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 9 table 7 shows the minimum current, in addition to i ccq , that is required by virtex-7 t and xt devices for proper power-on and configuration. if the current minimums shown in table 6 and table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. the fpga must not be configured until after v ccint is applied. once initialized and configured, us e the xilinx power tools to estimate current drain on these supplies. table 7: power-on current for virtex-7 t and xt devices device i ccintmin i ccauxmin i ccomin i ccaux_io i ccbram units xc7v585t i ccintq + 2700 i ccauxq +40 i ccoq + 60 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +108 ma xc7v2000t i ccintq + 4000 i ccauxq +80 i ccoq + 60 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +176 ma xc7vx330t i ccintq + 1000 i ccauxq +65 i ccoq + 40 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +95 ma xc7vx415t i ccintq + 1200 i ccauxq +75 i ccoq + 40 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +115 ma xc7vx485t i ccintq + 1200 i ccauxq +80 i ccoq + 40 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +140 ma xc7vx550t i ccintq + 3300 i ccauxq +143 i ccoq + 40 ma per bank i ccoauxioq + 57 ma per bank i ccbramq +200 ma xc7vx690t i ccintq + 3300 i ccauxq +143 i ccoq + 40 ma per bank i ccoauxioq + 57 ma per bank i ccbramq +200 ma XC7VX980T i ccintq + 6500 i ccauxq +202 i ccoq + 40 ma per bank i ccoauxioq + 60 ma per bank i ccbramq +204 ma xc7vx1140t i ccintq + 8000 i ccauxq +235 i ccoq + 40 ma per bank i ccoauxioq + 63 ma per bank i ccbramq +256 ma xq7v585t i ccintq + 2700 i ccauxq +40 i ccoq + 60 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +108 ma xq7vx330t i ccintq + 1000 i ccauxq +65 i ccoq + 40 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +95 ma xq7vx485t i ccintq + 1200 i ccauxq +80 i ccoq + 40 ma per bank i ccoauxioq + 40 ma per bank i ccbramq +140 ma xq7vx690t i ccintq + 3300 i ccauxq +143 i ccoq + 40 ma per bank i ccoauxioq + 57 ma per bank i ccbramq +200 ma xq7vx980t i ccintq + 6500 i ccauxq +202 i ccoq + 40 ma per bank i ccoauxioq + 60 ma per bank i ccbramq +204 ma table 8: power supply ramp time symbol description conditions min max units t vccint ramp time from gnd to 90% of v ccint 0.2 50 ms t vcco ramp time from gnd to 90% of v cco 0.2 50 ms t vccaux ramp time from gnd to 90% of v ccaux 0.2 50 ms t vccaux_io ramp time from gnd to 90% of v ccaux_io 0.2 50 ms t vccbram ramp time from gnd to 90% of v ccbram 0.2 50 ms t vcco2vccaux allowed time per power cycle for v cco ? v ccaux > 2.625v t j = 125c (1) ?300 ms t j = 100c (1) ?500 t j = 85c (1) ?800 t mgtavcc ramp time from gnd to 90% of v mgtavcc 0.2 50 ms t mgtavtt ramp time from gnd to 90% of v mgtavtt 0.2 50 ms t mgtvccaux ramp time from gnd to 90% of v mgtvccaux 0.2 50 ms notes: 1. based on 240,000 power cycles with nominal v cco of 3.3v or 36,500 power cycles with a worst case v cco of 3.465v. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 10 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. table 9: selectio dc input and output levels (1)(2) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8 ?8 hstl_i_12 ?0.300 v ref ?0.080 v ref + 0.080 v cco + 0.300 25% v cco 75% v cco 6.3 ?6.3 hstl_i_18 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8 ?8 hstl_ii ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16 ?16 hstl_ii_18 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16 ?16 hsul_12 ?0.300 v ref ?0.130 v ref + 0.130 v cco + 0.300 20% v cco 80% v cco 0.1 ?0.1 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ? 0.400 note 3 note 3 lvcmos15, lvdci_15 ?0.300 35% v cco 65% v cco v cco + 0.300 25% v cco 75% v cco note 4 note 4 lvcmos18, lvdci_18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvcmos25 ?0.300 0.700 1.700 v cco + 0.300 0.400 v cco ? 0.400 note 6 note 6 lvcmos33 ?0.300 0.800 2.000 3.450 0.400 v cco ? 0.400 note 6 note 6 lvttl ?0.300 0.800 2.000 3.450 0.400 2.400 note 7 note 7 mobile_ddr ?0.300 20% v cco 80% v cco v cco + 0.300 10% v cco 90% v cco 0.1 ?0.1 pci33_3 ?0.400 30% v cco 50% v cco v cco + 0.500 10% v cco 90% v cco 1.5 ?0.5 sstl12 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 14.25 ?14.25 sstl135 ?0.300 v ref ?0.090 v ref + 0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 13.0 ?13.0 sstl135_r ?0.300 v ref ?0.090 v ref + 0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 8.9 ?8.9 sstl15 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 13.0 ?13.0 sstl15_r ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 8.9 ?8.9 sstl18_i ?0.300 v ref ?0.125 v ref + 0.125 v cco + 0.300 v cco /2?0.470 v cco /2 + 0.470 8 ?8 sstl18_ii ?0.300 v ref ?0.125 v ref + 0.125 v cco + 0.300 v cco /2?0.600 v cco /2 + 0.600 13.4 ?13.4 notes: 1. tested according to relevant specifications. 2. 3.3v and 2.5v standards are only supported in 3.3v i/o banks. 3. supported drive strengths of 2, 4, 6, or 8 ma in hp i/o banks and 4, 8, or 12 ma in hr i/o banks. 4. supported drive strengths of 2, 4, 6, 8, 12, or 16 ma in hp i/o banks and 4, 8, 12, or 16 ma in hr i/o banks. 5. supported drive strengths of 2, 4, 6, 8, 12, or 16 ma in hp i/o banks and 4, 8, 12, 16, or 24 ma in hr i/o banks. 6. supported drive strengths of 4, 8, 12, or 16 ma 7. supported drive strengths of 4, 8, 12, 16, or 24 ma 8. for detailed interface specific dc voltage levels, see the 7 series fpgas selectio resources user guide ( ug471 ). s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 11 table 10: differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ocm (3) v od (4) v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max blvds_25 0.300 1.200 1.425 0.100 ? ? ? 1.250 ? note 5 mini_lvds_25 0.300 1.200 v ccaux 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 ppds_25 0.200 0.900 v ccaux 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 rsds_25 0.300 0.900 1.500 0.100 0.350 0. 600 1.000 1.200 1.400 0.100 0.350 0.600 tmds_33 2.700 2.965 3.230 0.150 0.675 1.200 v cco ?0.405 v cco ?0.300 v cco ?0.190 0.400 0.600 0.800 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ocm is the output common mode voltage. 4. v od is the output differential voltage (q ? q ). 5. v od for blvds will vary significantly depending on topology and loading. 6. lvds_25 is specified in table 12 . 7. lvds is specified in table 13 . table 11: complementary differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v, typ v, max v, min v, max v, max v, min ma, max ma, min diff_hstl_i 0.300 0.75 0 1.125 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_i_18 0.300 0. 900 1.425 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_ii 0.300 0.75 0 1.125 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hstl_ii_18 0.300 0. 900 1.425 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 diff_mobile_ddr 0.300 0.900 1.425 0.100 ? 10% v cco 90% v cco 0.100 ?0.100 diff_sstl12 0.300 0.600 0.850 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 14.25 ?14.25 diff_sstl135 0.300 0. 675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl135_r 0.300 0. 675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl15_r 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.00 ?8.00 diff_sstl18_ii 0.300 0. 900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 12 lvds dc specifications (lvds_25) the lvds standard is available in the hr i/o banks. lvds dc specifications (lvds) the lvds standard is available in the hp i/o banks. table 12: lvds_25 dc specifications (1) symbol dc parameter conditions min typ max units v cco supply voltage 2.375 2.500 2.625 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.700 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.000 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high 100 350 600 mv v icm input common-mode voltage 0.300 1.200 1.500 v notes: 1. differential inputs for lvds_25 can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7 series fpgas selectio resources user guide ( ug471 ) for more information. table 13: lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 1.710 1.800 1.890 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.825 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.000 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high common-mode input voltage = 1.25v 100 350 600 mv v icm input common-mode voltage differential input voltage = 350 mv 0.300 1.200 1.425 v notes: 1. differential inputs for lvds can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7series fpgas selectio resources user guide ( ug471 ) for more information. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 13 ac switching characteristics all values represented in this data sheet are based on the speed specifications in the ise? design suite 14.7 and vivado? design suite 2013.4 as outlined in table 14 . switching characteristics are specified on a per-speed-grade bas is and can be designated as advance, preliminary, or production. each designation is defined as follows: advance product specification these specifications are based on simula tions only and are typically available so on after device design specifications are frozen. although speed grades with this designation are consid ered relatively stable and conservative, some under- reporting might still occur. preliminary product specification these specifications ar e based on complete es (engineer ing sample) silicon characteriza tion. devices and speed grades with this designation are intended to gi ve a better indication of the expected performance of prod uction silicon. the probability of under-repo rting delays is greatly reduced as compared to advance data. production product specification these specifications ar e released once enough produc tion silicon of a part icular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal noti fication of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from measuring inte rnal test patterns. all ac switching characteristics are representative of worst-case supply voltage and junction temperature conditions. for more specific, more precise, and worst-case guaranteed da ta, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-7 t and xt fpgas. table 14: virtex-7 t and xt fpga speed sp ecification version by device version in: typical v ccint device ise 14.7 vivado 2013.4 ( table 2 ) 1.05 1.06 1.0v xq7v585t, xq7vx485t 1.06 1.07 1.0v xq7vx330t, xq7vx690t, xq7vx980t 1.10 1.11 1.0v xc7v585t, xc7vx485t n/a 1.10 1.0v xc7v2000t 1.10 1.11 1.0v xc7vx330t, xc7vx415t, xc7vx550t, xc7vx690t, XC7VX980T n/a 1.11 1.0v xc7vx1140t s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 14 speed grade designations since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. table 15 correlates the current status of each virtex-7 t and xt device on a per speed grade basis. production silicon and software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, produc tion). any labeling discrepancies are corrected in subsequent speed specification releases. table 16 lists the production released virtex-7 t and xt device , speed grade, and the minimum corresponding supported speed specification version and software revisions. the softwa re and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. table 15: virtex-7 t and xt device speed grade designations device speed grade designations advance prelimin ary production xc7v585t -3, -2, -2l, -1 xc7v2000t -2, -2l, -2g, -1 xc7vx330t -3, -2, -2l, -1 xc7vx415t -3, -2, -2l, -1 xc7vx485t -3, -2, -2l, -1 xc7vx550t -3, -2, -2l, -1 xc7vx690t -3, -2, -2l, -1 XC7VX980T -2, -2l, -1 xc7vx1140t -2, -2l, -2g, -1 xq7v585t -2, -2l, -1i, -1m xq7vx330t -2, -2l, -1i, -1m xq7vx485t -2i, -2l, -1i, -1m xq7vx690t -2i, -1i xq7vx980t -2l, -1i table 16: virtex-7 t and xt device production software and speed specification release device speed grade designations -3 -2g -2 -2l -1 -1m xc7v585t vivado tools 2012.4 v1.08 or ise tools 14.2 v1.06 n/a vivado tools 2012.4 v1.08 or ise tools 14.2 v1.06 n/a xc7v2000t n/a vivado tools 2012.4 v1.07 n/a xc7vx330t vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a xc7vx415t n/a n/a xc7vx485t vivado tools 2012.4 v1.08 or ise tools 14.2 v1.06 n/a vivado tools 2012.4 v1.08 or ise tools 14.2 v1.06 n/a xc7vx550t vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a xc7vx690t vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a XC7VX980T n/a n/a vivado tools 2013.1 v1.08 or ise tools 14.5 v1.08 n/a s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 15 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-7 t and xt devices. the numbers reported here are worst- case values; they have all been fully characterized. these values are subject to the same guidelines as the ac switching characteristics, page 13 . in each table, the i/o bank type is either high performance (hp) or high range (hr). table 18 provides the maximum data rates for applicable memory standards using the virtex-7 t and xt fpgas memory phy. the final performance of the memory interface is determined through a complete design implemented in the vivado or ise design suite, following guidelines in the zynq-7000 ap soc and 7 series devices memory interface solutions user guide ( ug586 ), electrical analysis, and characterization of the system. xc7vx1140t n/a vivado tools 2013.1 v1.08 n/a xq7v585t n/a n/a vivado tools 2013.1 v1.04 or ise tools 14.5 v1.04 xq7vx330t n/a n/a vivado tools 2013.1 v1.04 or ise tools 14.5 v1.04 vivado tools 2013.2 v1.05 or ise tools 14.6 v1.05 xq7vx485t n/a n/a vivado tools 2013.1 v1.04 or ise tools 14.5 v1.04 xq7vx690t n/a n/a vivado tools 2013.1 v1.04 or ise tools 14.5 v1.04 n/a vivado tools 2013.1 v1.04 or ise tools 14.5 v1.04 n/a xq7vx980t n/a n/a n/a vivado tools 2013.1 v1.04 or ise tools 14.5 v1.04 n/a table 17: networking applications interface performances description i/o bank type speed grade units -3 -2/-2l/-2g -1/-1m sdr lvds transmitter (using oserdes; data_width = 4 to 8) hr 710 710 625 mb/s hp 710 710 625 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 14) hr 1250 1250 950 mb/s hp 1600 1400 1250 mb/s sdr lvds receiver (sfi-4.1) (1) hr 710 710 625 mb/s hp 710 710 625 mb/s ddr lvds receiver (spi-4.2) (1) hr 1250 1250 950 mb/s hp 1600 1400 1250 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specific dynamic phase-alignment (dpa) algorithms domina te deterministic performance. table 16: virtex-7 t and xt device production software and speed specification release (cont?d) device speed grade designations -3 -2g -2 -2l -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 16 table 18: maximum physical interface (phy) rate for memory interfaces ip available with the memory interface generator (1)(2) memory standard i/o bank type v ccaux_io speed grade units -3 -2/-2l/-2g -1 -1m 4:1 memory controllers ddr3 hp 2.0v 1866 (3) 1866 (3) 1600 1066 mb/s hp 1.8v 1600 1333 1066 800 hr n/a 1066 1066 800 800 ddr3l hp 2.0v 1600 1600 1333 1066 mb/s hp 1.8v 1333 1066 800 800 hr n/a 800 800 667 n/a ddr2 hp 2.0v 800 800 800 667 mb/s hp 1.8v hr n/a 533 rldram iii hp 2.0v 800 667 667 550 mhz hp 1.8v 550 500 450 400 hr n/a n/a 2:1 memory controllers ddr3 hp 2.0v 1066 1066 800 667 mb/s hp 1.8v hr n/a ddr3l hp 2.0v 1066 1066 800 667 mb/s hp 1.8v hr n/a 800 800 667 n/a ddr2 hp 2.0v 800 800 800 667 mb/s hp 1.8v hr n/a 533 qdr ii+ (4) hp 2.0v 550 500 450 300 mhz hp 1.8v hr n/a 500 450 400 300 rldram ii hp 2.0v 533 500 450 400 mhz hp 1.8v hr n/a lpddr2 hp 2.0v 667 667 667 533 mb/s hp 1.8v hr n/a notes: 1. v ref tracking is required. for more information, see the zynq-7000 ap soc and 7 series devices memory interface solutions user guide ( ug586 ). 2. when using the internal v ref , the maximum data rate is 800 mb/s (400 mhz). 3. for designs using 1866 mb/s components, contact xilinx technical support . 4. the maximum qdrii+ performance specifications are for burst-le ngth 4 (bl = 4) implementations. burst length 2 (bl = 2) implementa tions are limited to 333 mhz for all speed grades and i/o bank types. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 17 iob pad input/output/3-state table 19 (3.3v high-range iob (hr)) and table 20 (1.8v high-performance iob (hp)) summarizes the values of standard- specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. ?t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on the capability of the selectio input buffer. ?t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of the selectio output buffer. ?t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depen ding on the selectio capability of the output buffer. in hp i/o banks, the internal dci termination turn-on time is always faster than t iotp when the dcitermdisable pin is used. in hr i/o banks, the in_term termination turn-on time is always faster than t iotp when the intermdisable pin is used. table 19: 3.3v iob high range (hr) switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m lvttl_s4 1.31 1.42 1.64 1.64 3.77 3.90 4.00 4.00 3.52 3.67 3.86 3.86 ns lvttl_s8 1.31 1.42 1.64 1.64 3.50 3.64 3.73 3.73 3.26 3.40 3.60 3.60 ns lvttl_s12 1.31 1.42 1.64 1.64 3.49 3.62 3.72 3.72 3.24 3.39 3.58 3.58 ns lvttl_s16 1.31 1.42 1.64 1.64 3.03 3.17 3.26 3.26 2.79 2.93 3.13 3.13 ns lvttl_s24 1.31 1.42 1.64 1.64 3.25 3.39 3.48 3.48 3.01 3.15 3.35 3.35 ns lvttl_f4 1.31 1.42 1.64 1.64 3.22 3.36 3.45 3.45 2.98 3.12 3.32 3.32 ns lvttl_f8 1.31 1.42 1.64 1.64 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns lvttl_f12 1.31 1.42 1.64 1.64 2.69 2.82 2.92 2.92 2.44 2.59 2.79 2.79 ns lvttl_f16 1.31 1.42 1.64 1.64 2.57 2.85 3.15 3.15 2.33 2.61 3.02 3.02 ns lvttl_f24 1.31 1.42 1.64 1.64 2.41 2.64 2.89 3.04 2.16 2.41 2.76 2.91 ns lvds_25 0.64 0.68 0.80 0.87 1.36 1.47 1.55 1.55 1.11 1.24 1.41 1.41 ns mini_lvds_25 0.68 0.70 0.79 0.87 1.36 1.47 1.55 1.55 1.11 1.24 1.41 1.41 ns blvds_25 0.65 0.69 0.80 0.85 1.83 2.02 2.20 2.57 1.59 1.79 2.07 2.44 ns rsds_25 (point to point) 0.63 0.68 0.79 0.87 1.36 1.48 1.55 1.55 1.11 1.24 1.41 1.41 ns ppds_25 0.65 0.69 0.80 0.87 1.36 1.49 1.58 1.58 1.11 1.25 1.45 1.45 ns tmds_33 0.72 0.76 0.86 0.90 1.43 1.54 1.60 1.60 1.18 1.31 1.47 1.47 ns pci33_3 1.28 1.41 1.65 1.65 2.71 3.08 3.52 3.52 2.46 2.84 3.39 3.39 ns hsul_12_s 0.63 0.64 0.71 0.85 1.77 1.90 2.00 2.00 1.52 1.67 1.86 1.86 ns hsul_12_f 0.63 0.64 0.71 0.85 1.26 1.40 1.50 1.50 1.01 1.16 1.37 1.37 ns diff_hsul_12_s 0.58 0.61 0.70 0.84 1.55 1.68 1.78 1.78 1.30 1.45 1.65 1.65 ns diff_hsul_12_f 0.58 0.61 0.70 0.84 1.16 1.28 1.35 1.35 0.92 1.04 1.21 1.21 ns mobile_ddr_s 0.64 0.66 0.74 0.74 2.58 2 .91 3.31 3.31 2.33 2.68 3.17 3.17 ns mobile_ddr_f 0.64 0.66 0.74 0.74 1.91 2 .13 2.36 2.36 1.66 1.89 2.23 2.23 ns diff_mobile_ddr_s 0.63 0.66 0.75 0.75 2.51 2.84 3.24 3.24 2.26 2.61 3.10 3.10 ns diff_mobile_ddr_f 0.63 0.66 0.75 0.75 1.89 2.11 2.34 2.34 1.64 1.88 2.21 2.21 ns hstl_i_s 0.61 0.64 0.73 0.84 1.55 1.69 1.80 1.80 1.30 1.46 1.67 1.67 ns hstl_ii_s 0.61 0.64 0.73 0.84 1.21 1.34 1.43 1.61 0.96 1.11 1.30 1.47 ns hstl_i_18_s 0.64 0.67 0.76 0.85 1.28 1.39 1.45 1.45 1.04 1.16 1.31 1.32 ns hstl_ii_18_s 0.64 0.67 0.76 0.85 1.18 1.31 1.40 1.57 0.93 1.08 1.27 1.44 ns s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 18 diff_hstl_i_s 0.63 0.67 0.77 0.84 1.42 1.54 1.61 1.78 1.17 1.31 1.48 1.65 ns diff_hstl_ii_s 0.63 0.67 0.77 0.84 1.15 1.24 1.27 1.61 0.91 1.01 1.14 1.47 ns diff_hstl_i_18_s 0.65 0.69 0.78 0.84 1.27 1.38 1.43 1.45 1.03 1.14 1.30 1.32 ns diff_hstl_ii_18_s 0.65 0.69 0.78 0.85 1.14 1.23 1.26 1.57 0.90 1.00 1.13 1.44 ns hstl_i_f 0.61 0.64 0.73 0.84 1.10 1.19 1.23 1.31 0.85 0.96 1.10 1.18 ns hstl_ii_f 0.61 0.64 0.73 0.84 1.05 1.18 1.28 1.31 0.80 0.95 1.15 1.18 ns hstl_i_18_f 0.64 0.67 0.76 0.85 1.05 1.18 1.28 1.36 0.80 0.95 1.15 1.22 ns hstl_ii_18_f 0.64 0.67 0.76 0.85 1.03 1.14 1.23 1.32 0.78 0.90 1.10 1.19 ns diff_hstl_i_f 0.63 0.67 0.77 0.84 1.09 1.18 1.22 1.31 0.84 0.95 1.09 1.18 ns diff_hstl_ii_f 0.63 0.67 0.77 0.84 1.02 1.11 1.14 1.31 0.77 0.88 1.01 1.18 ns diff_hstl_i_18_f 0.65 0.69 0.78 0.84 1.08 1.17 1.21 1.36 0.83 0.94 1.07 1.22 ns diff_hstl_ii_18_f 0.65 0.69 0.78 0.85 1.01 1.10 1.13 1.32 0.76 0.87 1.00 1.19 ns lvcmos33_s4 1.31 1.40 1.60 1.60 3.77 3.90 4.00 4.00 3.52 3.67 3.86 3.86 ns lvcmos33_s8 1.31 1.40 1.60 1.60 3.49 3.62 3.72 3.72 3.24 3.39 3.58 3.58 ns lvcmos33_s12 1.31 1.40 1.60 1.60 3.05 3.18 3.28 3.28 2.80 2.95 3.15 3.15 ns lvcmos33_s16 1.31 1.40 1.60 1.60 3.06 3.43 3.88 3.88 2.81 3.20 3.75 3.75 ns lvcmos33_f4 1.31 1.40 1.60 1.60 3.22 3.36 3.45 3.45 2.98 3.12 3.32 3.32 ns lvcmos33_f8 1.31 1.40 1.60 1.60 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns lvcmos33_f12 1.31 1.40 1.60 1.60 2.57 2.85 3.15 3.15 2.33 2.61 3.02 3.02 ns lvcmos33_f16 1.31 1.40 1.60 1.60 2.44 2.69 2.96 2.96 2.19 2.45 2.82 2.82 ns lvcmos25_s4 1.08 1.16 1.32 1.35 3.08 3.22 3.31 3.31 2.84 2.98 3.18 3.18 ns lvcmos25_s8 1.08 1.16 1.32 1.35 2.85 2.98 3.07 3.08 2.60 2.75 2.94 2.94 ns lvcmos25_s12 1.08 1.16 1.32 1.35 2.44 2.57 2.67 2.67 2.19 2.34 2.54 2.54 ns lvcmos25_s16 1.08 1.16 1.32 1.35 2.79 2.92 3.01 3.01 2.54 2.68 2.88 2.88 ns lvcmos25_f4 1.08 1.16 1.32 1.35 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns lvcmos25_f8 1.08 1.16 1.32 1.35 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns lvcmos25_f12 1.08 1.16 1.32 1.35 2.15 2.29 2.52 2.52 1.91 2.05 2.38 2.38 ns lvcmos25_f16 1.08 1.16 1.32 1.35 1.92 2.17 2.45 2.45 1.67 1.94 2.32 2.32 ns lvcmos18_s4 0.64 0.66 0.74 0.95 1.55 1.68 1.78 1.78 1.30 1.45 1.65 1.65 ns lvcmos18_s8 0.64 0.66 0.74 0.95 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns lvcmos18_s12 0.64 0.66 0.74 0.95 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns lvcmos18_s16 0.64 0.66 0.74 0.95 1.49 1.62 1.72 1.72 1.24 1.39 1.58 1.58 ns lvcmos18_s24 0.64 0.66 0.74 0.95 1.74 1.92 2.08 2.22 1.50 1.69 1.95 2.08 ns lvcmos18_f4 0.64 0.66 0.74 0.95 1.38 1.51 1.61 1.64 1.13 1.28 1.47 1.50 ns lvcmos18_f8 0.64 0.66 0.74 0.95 1.64 1.78 1.87 1.87 1.40 1.54 1.74 1.74 ns lvcmos18_f12 0.64 0.66 0.74 0.95 1.64 1.78 1.87 1.87 1.40 1.54 1.74 1.74 ns lvcmos18_f16 0.64 0.66 0.74 0.95 1.52 1.68 1.81 1.81 1.28 1.45 1.68 1.68 ns lvcmos18_f24 0.64 0.66 0.74 0.95 1.34 1.46 1.55 2.09 1.09 1.23 1.42 1.96 ns lvcmos15_s4 0.66 0.69 0.81 0.93 1.86 2.00 2.09 2.09 1.62 1.76 1.96 1.96 ns lvcmos15_s8 0.66 0.69 0.81 0.93 2.05 2.18 2.28 2.28 1.80 1.95 2.14 2.15 ns table 19: 3.3v iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 19 lvcmos15_s12 0.66 0.69 0.81 0.93 1.83 2.03 2.23 2.23 1.59 1.80 2.10 2.10 ns lvcmos15_s16 0.66 0.69 0.81 0.93 1.76 1.95 2.13 2.13 1.52 1.72 1.99 1.99 ns lvcmos15_f4 0.66 0.69 0.81 0.93 1.63 1.76 1.86 1.86 1.38 1.53 1.72 1.72 ns lvcmos15_f8 0.66 0.69 0.81 0.93 1.79 1.99 2.18 2.18 1.55 1.76 2.05 2.05 ns lvcmos15_f12 0.66 0.69 0.81 0.93 1.40 1.54 1.65 1.65 1.15 1.31 1.52 1.52 ns lvcmos15_f16 0.66 0.69 0.81 0.93 1.37 1.51 1.61 1.89 1.13 1.27 1.48 1.75 ns lvcmos12_s4 0.88 0.91 1.00 1.17 2.53 2.67 2.76 2.76 2.29 2.43 2.63 2.63 ns lvcmos12_s8 0.88 0.91 1.00 1.17 2.05 2.18 2.28 2.28 1.80 1.95 2.14 2.15 ns lvcmos12_s12 0.88 0.91 1.00 1.17 1.75 1.89 1.98 1.98 1.51 1.65 1.85 1.85 ns lvcmos12_f4 0.88 0.91 1.00 1.17 1.94 2.07 2.17 2.17 1.69 1.84 2.04 2.04 ns lvcmos12_f8 0.88 0.91 1.00 1.17 1.50 1.64 1.73 1.73 1.26 1.40 1.60 1.60 ns lvcmos12_f12 0.88 0.91 1.00 1.17 1.54 1.71 1.87 1.87 1.29 1.48 1.74 1.74 ns sstl135_s 0.61 0.64 0.73 0.85 1.27 1.40 1.50 1.53 1.02 1.17 1.36 1.40 ns sstl15_s 0.61 0.64 0.73 0.73 1.24 1.37 1.47 1.53 0.99 1.14 1.33 1.40 ns sstl18_i_s 0.64 0.67 0.76 0.84 1.59 1.74 1.85 1.85 1.34 1.50 1.72 1.72 ns sstl18_ii_s 0.64 0.67 0.76 0.85 1.27 1.40 1.50 1.50 1.02 1.17 1.36 1.36 ns diff_sstl135_s 0.59 0.61 0.73 0.85 1.27 1.40 1.50 1.53 1.02 1.17 1.36 1.40 ns diff_sstl15_s 0.63 0.67 0.77 0.85 1.24 1.37 1.47 1.53 0.99 1.14 1.33 1.40 ns diff_sstl18_i_s 0.65 0.69 0.78 0.85 1.50 1.63 1.72 1.82 1.26 1.40 1.59 1.69 ns diff_sstl18_ii_s 0.65 0.69 0.78 0.85 1.13 1.22 1.25 1.50 0.88 0.99 1.12 1.36 ns sstl135_f 0.61 0.64 0.73 0.85 1.04 1.17 1.26 1.31 0.79 0.93 1.13 1.18 ns sstl15_f 0.61 0.64 0.73 0.73 1.04 1.17 1.26 1.26 0.79 0.93 1.13 1.13 ns sstl18_i_f 0.64 0.67 0.76 0.84 1.12 1.22 1.26 1.34 0.88 0.99 1.13 1.21 ns sstl18_ii_f 0.64 0.67 0.76 0.85 1.05 1.18 1.28 1.32 0.80 0.95 1.15 1.19 ns diff_sstl135_f 0.59 0.61 0.73 0.85 1.04 1.17 1.26 1.31 0.79 0.93 1.13 1.18 ns diff_sstl15_f 0.63 0.67 0.77 0.85 1.04 1.17 1.26 1.26 0.79 0.93 1.13 1.13 ns diff_sstl18_i_f 0.65 0.69 0.78 0.85 1.10 1.19 1.23 1.34 0.85 0.96 1.10 1.21 ns diff_sstl18_ii_f 0.65 0.69 0.78 0.85 1.02 1.10 1.14 1.32 0.77 0.87 1.00 1.19 ns table 19: 3.3v iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 20 table 20: 1.8v iob high performance (hp) switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m lvds 0.75 0.79 0.92 0.96 1.05 1.17 1.24 1.26 0.88 1.01 1.08 1.10 ns hsul_12_s 0.69 0.72 0.82 0.98 1.65 1.84 2.05 2.05 1.48 1.68 1.89 1.89 ns hsul_12_f 0.69 0.72 0.82 0.98 1.39 1.54 1.68 1.68 1.22 1.38 1.52 1.52 ns diff_hsul_12_s 0.69 0.72 0.82 0.98 1.65 1.84 2.05 2.05 1.48 1.68 1.89 1.89 ns diff_hsul_12_f 0.69 0.72 0.82 0.98 1.39 1.54 1.68 1.68 1.22 1.38 1.52 1.52 ns diff_hsul_12_dci_s 0.69 0.72 0.82 0.82 1.78 1.91 2.05 2.05 1.61 1.76 1.89 1.89 ns diff_hsul_12_dci_f 0.69 0.72 0.82 0.82 1.56 1.67 1.76 1.76 1.39 1.51 1.60 1.60 ns hstl_i_s 0.68 0.72 0.82 0.90 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns hstl_ii_s 0.68 0.72 0.82 0.90 1.05 1.17 1.26 1.27 0.88 1.01 1.10 1.11 ns hstl_i_18_s 0.70 0.72 0.82 0.95 1.12 1.24 1.34 1.34 0.95 1.08 1.18 1.18 ns hstl_ii_18_s 0.70 0.72 0.82 0.90 1.06 1.18 1.26 1.27 0.89 1.02 1.10 1.11 ns hstl_i_12_s 0.68 0.72 0.82 0.96 1.14 1.27 1.37 1.37 0.97 1.11 1.21 1.21 ns hstl_i_dci_s 0.68 0.72 0.82 0.90 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns hstl_ii_dci_s 0.68 0.72 0.82 0.85 1.05 1.17 1.26 1.26 0.88 1.01 1.10 1.10 ns hstl_ii_t_dci_s 0.70 0.72 0.82 0.82 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns hstl_i_dci_18_s 0.70 0.72 0.82 0.90 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns hstl_ii_dci_18_s 0.70 0.72 0.82 0.82 1.05 1.16 1.24 1.24 0.88 1.00 1.08 1.08 ns hstl_ii _t_dci_18_s 0.70 0.72 0.82 0.84 1.11 1.23 1.33 1.34 0.94 1.07 1.17 1.18 ns diff_hstl_i_s 0.75 0.79 0.92 1.02 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns diff_hstl_ii_s 0.75 0.79 0.92 1.02 1.05 1.17 1.26 1.32 0.88 1.01 1.10 1.16 ns diff_hstl_i_dci_s 0.75 0.79 0.92 0.92 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns diff_hstl_ii_dci_s 0.75 0.79 0.92 0.92 1.05 1.17 1.26 1.26 0.88 1.01 1.10 1.10 ns diff_hstl_i_18_s 0.75 0.79 0.92 0.98 1.12 1.24 1.34 1.34 0.95 1.08 1.18 1.18 ns diff_hstl_ii_18_s 0.75 0.79 0.92 0.99 1.06 1.18 1.26 1.32 0.89 1.02 1.10 1.16 ns diff_hstl_i_dci_18_s 0.75 0.79 0.92 0.92 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns diff_hstl_ii_dci_18_s 0.75 0.79 0.92 0.93 1.05 1.16 1.24 1.26 0.88 1.00 1.08 1.10 ns diff_hstl_ii _t_dci_18_s 0.75 0.79 0.92 0.92 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns hstl_i_f 0.68 0.72 0.82 0.90 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns hstl_ii_f 0.68 0.72 0.82 0.90 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns hstl_i_18_f 0.70 0.72 0.82 0.95 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns hstl_ii_18_f 0.70 0.72 0.82 0.90 0.98 1.09 1.16 1.20 0.81 0.94 1.00 1.03 ns hstl_i_12_f 0.68 0.72 0.82 0.96 1.02 1.13 1.21 1.21 0.85 0.97 1.05 1.05 ns hstl_i_dci_f 0.68 0.72 0.82 0.90 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns hstl_ii_dci_f 0.68 0.72 0.82 0.85 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns hstl_ii_t_dci_f 0.70 0.72 0.82 0.82 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns hstl_i_dci_18_f 0.70 0.72 0.82 0.90 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns hstl_ii_dci_18_f 0.70 0.72 0.82 0.82 0.98 1.09 1.16 1.16 0.81 0.93 1.00 1.00 ns hstl_ii _t_dci_18_f 0.70 0.72 0.82 0.84 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns diff_hstl_i_f 0.75 0.79 0.92 1.02 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 21 diff_hstl_ii_f 0.75 0.79 0.92 1.02 0.97 1.08 1.15 1.20 0.80 0.92 0.99 1.03 ns diff_hstl_i_dci_f 0.75 0.79 0.92 0.92 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns diff_hstl_ii_dci_f 0.75 0.79 0.92 0.92 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns diff_hstl_i_18_f 0.75 0.79 0.92 0.98 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns diff_hstl_ii_18_f 0.75 0.79 0.92 0.99 0.98 1.09 1.16 1.24 0.81 0.94 1.00 1.08 ns diff_hstl_i_dci_18_f 0.75 0.79 0.92 0.92 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns diff_hstl_ii_dci_18_f 0.75 0.79 0.92 0.93 0.98 1.09 1.16 1.18 0.81 0.93 1.00 1.02 ns diff_hstl_ii _t_dci_18_f 0.75 0.79 0.92 0.92 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns lvcmos18_s2 0.47 0.50 0.60 0.90 3.95 4.28 4.85 4.85 3.78 4.13 4.69 4.69 ns lvcmos18_s4 0.47 0.50 0.60 0.90 2.67 2.98 3.43 3.43 2.50 2.82 3.27 3.27 ns lvcmos18_s6 0.47 0.50 0.60 0.90 2.14 2.38 2.72 2.72 1.97 2.22 2.56 2.56 ns lvcmos18_s8 0.47 0.50 0.60 0.90 1.98 2.21 2.52 2.52 1.81 2.05 2.36 2.36 ns lvcmos18_s12 0.47 0.50 0.60 0.90 1.70 1.91 2.17 2.17 1.53 1.75 2.01 2.01 ns lvcmos18_s16 0.47 0.50 0.60 0.90 1.57 1.75 1.97 1.97 1.40 1.59 1.81 1.81 ns lvcmos18_f2 0.47 0.50 0.60 0.90 3.50 3.87 4.48 4.48 3.33 3.71 4.32 4.32 ns lvcmos18_f4 0.47 0.50 0.60 0.90 2.23 2.50 2.87 2.87 2.06 2.34 2.71 2.71 ns lvcmos18_f6 0.47 0.50 0.60 0.90 1.80 2.00 2.26 2.26 1.63 1.84 2.09 2.09 ns lvcmos18_f8 0.47 0.50 0.60 0.90 1.46 1.72 2.04 2.04 1.29 1.56 1.88 1.88 ns lvcmos18_f12 0.47 0.50 0.60 0.90 1.26 1.40 1.53 1.53 1.09 1.24 1.37 1.37 ns lvcmos18_f16 0.47 0.50 0.60 0.90 1.19 1.33 1.44 1.66 1.02 1.17 1.28 1.50 ns lvcmos15_s2 0.59 0.62 0.73 0.88 3.55 3.89 4.45 4.45 3.38 3.73 4.29 4.29 ns lvcmos15_s4 0.59 0.62 0.73 0.88 2.45 2.70 3.06 3.06 2.28 2.54 2.90 2.90 ns lvcmos15_s6 0.59 0.62 0.73 0.88 2.24 2.51 2.88 2.88 2.07 2.35 2.72 2.72 ns lvcmos15_s8 0.59 0.62 0.73 0.88 1.91 2.16 2.49 2.49 1.74 2.00 2.32 2.32 ns lvcmos15_s12 0.59 0.62 0.73 0.88 1.77 1.98 2.23 2.23 1.60 1.82 2.07 2.07 ns lvcmos15_s16 0.59 0.62 0.73 0.88 1.62 1.81 2.02 2.02 1.45 1.65 1.86 1.86 ns lvcmos15_f2 0.59 0.62 0.73 0.88 3.38 3.69 4.18 4.18 3.21 3.53 4.02 4.02 ns lvcmos15_f4 0.59 0.62 0.73 0.88 2.04 2.21 2.44 2.44 1.87 2.06 2.27 2.27 ns lvcmos15_f6 0.59 0.62 0.73 0.88 1.47 1.74 2.09 2.09 1.30 1.58 1.93 1.93 ns lvcmos15_f8 0.59 0.62 0.73 0.88 1.31 1.46 1.61 1.61 1.14 1.30 1.45 1.45 ns lvcmos15_f12 0.59 0.62 0.73 0.88 1.21 1.34 1.45 1.45 1.04 1.18 1.29 1.29 ns lvcmos15_f16 0.59 0.62 0.73 0.88 1.18 1.31 1.41 1.68 1.01 1.15 1.25 1.52 ns lvcmos12_s2 0.64 0.67 0.78 1.04 3.38 3.80 4.48 4.48 3.21 3.64 4.31 4.31 ns lvcmos12_s4 0.64 0.67 0.78 1.04 2.62 2.94 3.43 3.43 2.45 2.78 3.27 3.27 ns lvcmos12_s6 0.64 0.67 0.78 1.04 2.05 2.33 2.72 2.72 1.88 2.17 2.56 2.56 ns lvcmos12_s8 0.64 0.67 0.78 1.04 1.94 2.18 2.51 2.51 1.77 2.02 2.34 2.34 ns lvcmos12_f2 0.64 0.67 0.78 1.04 2.84 3.15 3.62 3.62 2.67 2.99 3.46 3.46 ns lvcmos12_f4 0.64 0.67 0.78 1.04 1.97 2.18 2.44 2.44 1.80 2.02 2.28 2.28 ns lvcmos12_f6 0.64 0.67 0.78 1.04 1.33 1.51 1.70 1.70 1.16 1.35 1.54 1.54 ns lvcmos12_f8 0.64 0.67 0.78 1.04 1.27 1.42 1.55 1.55 1.10 1.26 1.39 1.39 ns table 20: 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 22 lvdci_18 0.47 0.50 0.60 0.87 1.99 2.15 2.35 2.35 1.82 1.99 2.19 2.19 ns lvdci_15 0.59 0.62 0.73 0.92 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns lvdci_dv2_18 0.47 0.50 0.60 0.88 1.99 2.15 2.34 2.34 1.82 1.99 2.18 2.18 ns lvdci_dv2_15 0.59 0.62 0.73 0.88 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns hslvdci_18 0.68 0.72 0.82 0.90 1.99 2.15 2.35 2.35 1.82 1.99 2.19 2.19 ns hslvdci_15 0.68 0.72 0.82 0.93 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns sstl18_i_s 0.68 0.72 0.82 0.95 1.02 1.15 1.24 1.24 0.85 0.99 1.08 1.08 ns sstl18_ii_s 0.68 0.72 0.82 1.01 1.17 1.29 1.37 1.38 1.00 1.13 1.21 1.22 ns sstl18_i_dci_s 0.68 0.72 0.82 0.87 0.92 1.06 1.17 1.18 0.75 0.90 1.01 1.02 ns sstl18_ii_dci_s 0.68 0.72 0.82 0.82 0.88 0.98 1.08 1.12 0.71 0.83 0.92 0.96 ns sstl18_ii_t_dci_s 0.68 0.72 0.82 0.98 0.92 1.06 1.17 1.18 0.75 0.90 1.01 1.02 ns sstl15_s 0.68 0.72 0.82 0.82 0.94 1.06 1.15 1.16 0.77 0.91 0.99 1.00 ns sstl15_dci_s 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.16 0.77 0.90 0.99 1.00 ns sstl15_t_dci_s 0.68 0.72 0.82 0.87 0.94 1.06 1.15 1.15 0.77 0.90 0.99 0.99 ns sstl135_s 0.69 0.72 0.82 0.93 0.97 1.10 1.19 1.20 0.80 0.94 1.03 1.03 ns sstl135_dci_s 0.69 0.72 0.82 0.85 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns sstl135_t_dci_s 0.69 0.72 0.82 0.93 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns sstl12_s 0.69 0.72 0.82 1.02 0.96 1.09 1.18 1.18 0.79 0.93 1.02 1.02 ns sstl12_dci_s 0.69 0.72 0.82 0.90 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns sstl12_t_dci_s 0.69 0.72 0.82 0.88 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns diff_sstl18_i_s 0.75 0.79 0.92 0.99 1.02 1.15 1.24 1.29 0.85 0.99 1.08 1.13 ns diff_sstl18_ii_s 0.75 0.79 0.92 0.93 1.17 1.29 1.37 1.40 1.00 1.13 1.21 1.24 ns diff_sstl18_i_dci_s 0.75 0.79 0.92 0.92 0.92 1.06 1.17 1.24 0.75 0.90 1.01 1.08 ns diff_sstl18_ii_dci_s 0.75 0.79 0.92 0.96 0.88 0.98 1.08 1.18 0.71 0.83 0.92 1.02 ns diff_sstl18_ii_t_dci_s 0.75 0.79 0.92 0.92 0.92 1.06 1.17 1.24 0.75 0.90 1.01 1.08 ns diff_sstl15_s 0.68 0.72 0.82 0.99 0.94 1.06 1.15 1.16 0.77 0.91 0.99 1.00 ns diff_sstl15_dci_s 0.68 0.72 0.82 0.96 0.94 1.06 1.15 1.16 0.77 0.90 0.99 1.00 ns diff_sstl15_t_dci_s 0.68 0.72 0.82 0.88 0.94 1.06 1.15 1.23 0.77 0.90 0.99 1.07 ns diff_sstl135_s 0.69 0.72 0.82 1.09 0.97 1.10 1.19 1.20 0.80 0.94 1.03 1.03 ns diff_sstl135_dci_s 0.69 0.72 0.82 0.90 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns diff_sstl135_t_dci_s 0.69 0.72 0.82 0.84 0.97 1.09 1.19 1.27 0.80 0.93 1.03 1.11 ns diff_sstl12_s 0.69 0.72 0.82 0.96 0.96 1.09 1.18 1.18 0.79 0.93 1.02 1.02 ns diff_sstl12_dci_s 0.69 0.72 0.82 0.87 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns diff_sstl12_t_dci_s 0.69 0.72 0.82 0.96 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns sstl18_i_f 0.68 0.72 0.82 0.95 0.94 1.06 1.15 1.15 0.77 0.91 0.99 0.99 ns sstl18_ii_f 0.68 0.72 0.82 1.01 0.97 1.09 1.16 1.21 0.80 0.93 1.00 1.05 ns sstl18_i_dci_f 0.68 0.72 0.82 0.87 0.89 1.02 1.10 1.15 0.72 0.86 0.94 0.99 ns sstl18_ii_dci_f 0.68 0.72 0.82 0.82 0.89 1.02 1.10 1.10 0.72 0.86 0.94 0.94 ns sstl18_ii_t_dci_f 0.68 0.72 0.82 0.98 0.89 1.02 1.10 1.15 0.72 0.86 0.94 0.99 ns sstl15_f 0.68 0.72 0.82 0.82 0.89 1.01 1.09 1.09 0.72 0.85 0.93 0.93 ns table 20: 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 23 table 21 specifies the values of t iotphz and t ioibufdisable . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). t ioibufdisable is described as the iob delay from ibufdisable to o output. in hp i/o banks, the internal dci termination turn -off time is always faster than t iotphz when the dcitermdisable pin is used. in hr i/o banks, the internal in_term termin ation turn-off time is always faster than t iotphz when the intermdisable pin is used. sstl15_dci_f 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns sstl15_t_dci_f 0.68 0.72 0.82 0.87 0.89 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns sstl135_f 0.69 0.72 0.82 0.93 0.88 1.00 1.08 1.12 0.71 0.85 0.92 0.96 ns sstl135_dci_f 0.69 0.72 0.82 0.85 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns sstl135_t_dci_f 0.69 0.72 0.82 0.93 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns sstl12_f 0.69 0.72 0.82 1.02 0.88 1.00 1.08 1.12 0.71 0.84 0.92 0.96 ns sstl12_dci_f 0.69 0.72 0.82 0.90 0.91 1.03 1.11 1.11 0.74 0.88 0.95 0.95 ns sstl12_t_dci_f 0.69 0.72 0.82 0.88 0.91 1.03 1.11 1.12 0.74 0.88 0.95 0.96 ns diff_sstl18_i_f 0.75 0.79 0.92 0.99 0.94 1.06 1.15 1.23 0.77 0.91 0.99 1.07 ns diff_sstl18_ii_f 0.75 0.79 0.92 0.93 0.97 1.09 1.16 1.24 0.80 0.93 1.00 1.08 ns diff_sstl18_i_dci_f 0.75 0.79 0.92 0.92 0.89 1.02 1.10 1.23 0.72 0.86 0.94 1.07 ns diff_sstl18_ii_dci_f 0.75 0.79 0.92 0.96 0.89 1.02 1.10 1.16 0.72 0.86 0.94 1.00 ns diff_sstl18_ii_t_dci_f 0.75 0.79 0.92 0.92 0.89 1.02 1.10 1.24 0.72 0.86 0.94 1.08 ns diff_sstl15_f 0.68 0.72 0.82 0.99 0.89 1.01 1.09 1.09 0.72 0.85 0.93 0.93 ns diff_sstl15_dci_f 0.68 0.72 0.82 0.96 0.89 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns diff_sstl15_t_dci_f 0.68 0.72 0.82 0.88 0.89 1.01 1.09 1.20 0.72 0.85 0.93 1.03 ns diff_sstl135_f 0.69 0.72 0.82 1.09 0.88 1.00 1.08 1.12 0.71 0.85 0.92 0.96 ns diff_sstl135_dci_f 0.69 0.72 0.82 0.90 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns diff_sstl135_t_dci_f 0.69 0.72 0.82 0.84 0.89 1.00 1.08 1.20 0.72 0.85 0.92 1.03 ns diff_sstl12_f 0.69 0.72 0.82 0.96 0.88 1.00 1.08 1.12 0.71 0.84 0.92 0.96 ns diff_sstl12_dci_f 0.69 0.72 0.82 0.87 0.91 1.03 1.11 1.11 0.74 0.88 0.95 0.95 ns diff_sstl12_t_dci_f 0.69 0.72 0.82 0.96 0.91 1.03 1.11 1.18 0.74 0.88 0.95 1.02 ns table 21: iob 3-state output switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m t iotphz t input to pad high-impedance 0.76 0.86 0.99 0.99 ns t ioibufdisable_hr ibuf turn-on time from ibufdisable to o output for hr i/o banks 1.72 1.89 2.14 2.14 ns t ioibufdisable_hp ibuf turn-on time from ibufdisable to o output for hp i/o banks 1.31 1.46 1.76 1.76 ns table 20: 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 24 i/o standard adjustment measurement methodology input delay measurements table 22 shows the test setup parameters used for measuring input delay. table 22: input delay measurement methodology description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, 1.5v lvcmos15 0.1 1.4 0.75 ? lvcmos, 1.8v lvcmos18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.65 ? lvttl, 3.3v lvttl 0.1 3.2 1.65 ? mobile_ddr, 1.8v mobile_ddr 0.1 1.7 0.9 ? pci33, 3.3v pci33_3 0.1 3.2 1.65 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.60 hstl, class i & ii, 1.5v hstl_i, hstl_ii v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.8 v ref +0.8 v ref 0.90 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl (stub terminated transceiver logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl, 1.35v sstl135, sstl135_r v ref ? 0.575 v ref + 0.575 v ref 0.675 sstl, 1.5v sstl15, sstl15_r v ref ?0.65 v ref +0.65 v ref 0.75 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.90 diff_mobile_ddr, 1.8v diff_mo bile_ddr 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hstl, class i, 1.2v di ff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_hstl, class i & ii,1.5v diff_hstl_i, diff_hstl_ii 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_hstl, class i & ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hsul, 1.2v diff_hsul _12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl, 1.2v diff_sst l12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl135/dif f_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 0.675 ? 0.125 0.675 + 0.125 0 (6) ? diff_sstl15/diff _sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_sstl18_i/di ff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (6) ? lvds (low-voltage differential si gnaling), 1.8v lvds 0. 9 ? 0.125 0.9 + 0.125 0 (6) ? lvds_25, 2.5v lvds_2 5 1.2 ? 0.125 1.2 + 0.125 0 (6) ? blvds_25, 2.5v blvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? mini_lvds_25, 2.5v mini_lvds _25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? ppds_25 ppds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? rsds_25 rsds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 25 output delay measurements output delays are measured with short output traces. standard termination was used for all testing. the propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 1 and figure 2 . parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from table 23 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . tmds_33 tmds_33 3 ? 0.125 3 + 0.125 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as fo r hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 1 . 6. the value given is the differential input voltage. x-ref target - figure 1 figure 1: single-ended test setup x-ref target - figure 2 figure 2: differential test setup table 22: input delay measurement methodology (cont?d) description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 1 83 _06_010716 r ref v mea s + ? c ref fpga o u tp u t d s 1 83 _07_010716 s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 26 5. compare the results of step 2 and step 4 . the increase or decrease in delay yields the actual propagation delay of the pcb trace. table 23: output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos/lvdci/hslvdci, 1.5v lvcmos 15, lvdci_15, hslvdci_15 1m 0 0.75 0 lvcmos/lvdci/hslvdci, 1.8v lvcmos 18, lvdci_15, hslvdci_18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 pci33, 3.3v pci33_3 25 10 1.65 0 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class ii, 1.5v hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12, 1.2v sstl12 50 0 v ref 0.6 sstl135/sstl135_r, 1.35v sstl135, sstl135_r 50 0 v ref 0.675 sstl15/sstl15_r, 1.5v sstl15, sstl15_r 50 0 v ref 0.75 sstl (stub series terminated logic), class i & class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 diff_mobile_ddr, 1.8v diff_mobile_ddr 50 0 v ref 0.9 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i & ii, 1.5v diff_hstl_i, diff_hstl_ii 50 0 v ref 0.75 diff_hstl, class i & ii, 1.8v diff _hstl_i_18, diff_hstl_ii_18 50 0 v ref 0.9 diff_hsul_12, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl12, 1.2v diff_sstl12 50 0 v ref 0.6 diff_sstl135/diff_sst l135_r, 1.35v diff_sstl135, diff_sstl135_r 50 0 v ref 0.675 diff_sstl15/diff_ sstl15_r, 1.5v diff_sstl1 5, diff_sstl15_r 50 0 v ref 0.75 diff_sstl18, class i & ii, 1.8v di ff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 lvds (low-voltage differenti al signaling), 1.8v lvds 100 0 0 (2) 0 lvds, 2.5v lvds_25 100 0 0 (2) 0 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 mini lvds, 2.5v mini_lvds_25 100 0 0 (2) 0 ppds_25 ppds_25 100 0 0 (2) 0 rsds_25 rsds_25 100 0 0 (2) 0 tmds_33 tmds_33 50 0 0 (2) 3.3 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 27 input/output logic switching characteristics table 24: ilogic switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to cl k 0.42/0.00 0.48/0.00 0. 67/0.00 0.67/0.00 ns t isrck /t icksr sr pin setup/hold with respect to cl k 0.53/0.01 0.61/0.01 0. 99/0.01 0.99/0.01 ns t idocke2 /t iockde2 d pin setup/hold with respect to clk without delay (hp i/o banks only) 0.01/0.27 0.01/0.29 0. 01/0.34 0.01/0.34 ns t idockde2 /t iockdde2 ddly pin setup/hold with respect to clk (using idelay) (hp i/o banks only) 0.01/0.27 0.02/0.29 0. 02/0.34 0.02/0.34 ns t idocke3 /t iockde3 d pin setup/hold with respect to clk without delay (hr i/o banks only) 0.01/0.27 0.01/0.29 0. 01/0.34 0.01/0.34 ns t idockde3 /t iockdde3 ddly pin setup/hold with respect to clk (using idelay) (hr i/o banks only) 0.01/0.27 0.02/0.29 0. 02/0.34 0.02/0.34 ns combinatorial t idie2 d pin to o pin propagation delay, no delay (hp i/o banks only) 0.09 0.10 0.12 0.12 ns t idide2 ddly pin to o pin propagation delay (using idelay) (hp i/o banks only) 0.10 0.11 0.13 0.13 ns t idie3 d pin to o pin propagation delay, no delay (hr i/o banks only) 0.09 0.10 0.12 0.12 ns t idide3 ddly pin to o pin propagation delay (using idelay) (hr i/o banks only) 0.10 0.11 0.13 0.13 ns sequential delays t idloe2 d pin to q1 pin using flip-flop as a latch without delay (hp i/o banks only) 0.36 0.39 0.45 0.45 ns t idlode2 ddly pin to q1 pin using flip-flop as a latch (using idelay) (hp i/o banks only) 0.36 0.39 0.45 0.45 ns t idloe3 d pin to q1 pin using flip-flop as a latch without delay (hr i/o banks only) 0.36 0.39 0.45 0.45 ns t idlode3 ddly pin to q1 pin using flip-flop as a latch (using idelay) (hr i/o banks only) 0.36 0.39 0.45 0.45 ns t ickq clk to q outputs 0.47 0.50 0.58 0.58 ns t rq_ilogice2 sr pin to oq/tq out (hp i/o banks only) 0.84 0.94 1.16 1.16 ns t gsrq_ilogice2 global set/reset to q outputs (hp i/o banks only) 7.60 7.60 10.51 10.51 ns t rq_ilogice3 sr pin to oq/tq out (hr i/o banks only) 0.84 0.94 1.16 1.16 ns t gsrq_ilogice3 global set/reset to q outputs (hr i/o banks only) 7.60 7.60 10.51 10.51 ns set/reset t rpw_ilogice2 minimum pulse width, sr inputs (hp i/o banks only) 0.54 0.63 0.63 0.63 ns, min t rpw_ilogice3 minimum pulse width, sr inputs (hr i/o banks only) 0.54 0.63 0.63 0.63 ns, min s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 28 table 25: ologic switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0 .45/?0.13 0.50/?0.13 0 .58/?0.13 0.58/?0.13 ns t ooceck /t ockoce oce pin setup/hold with respect to cl k 0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 ns t osrck /t ocksr sr pin setup/hold with respect to clk 0.32/0.18 0.38/0.18 0.70/0.18 0.70/0.18 ns t otck /t ockt t1/t2 pins setup/hold with respect to cl k 0.49/?0.16 0.56/?0.16 0 .68/?0.16 0.68/?0.13 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.06 ns combinatorial t odq d1 to oq out or t1 to tq out 0.73 0.81 0.97 0.97 ns sequential delays t ockq clk to oq/tq out 0.41 0.43 0.49 0.49 ns t rq_ologice2 sr pin to oq/tq out (hp i/o banks only) 0.63 0.70 0.83 0.83 ns t gsrq_ologice2 global set/reset to q outputs (hp i/o banks only) 7.60 7.60 10.51 10.51 ns t rq_ologice3 sr pin to oq/tq out (hr i/o banks only) 0.63 0.70 0.83 0.83 ns t gsrq_ologice3 global set/reset to q outputs (hr i/o banks only) 7.60 7.60 10.51 10.51 ns set/reset t rpw_ologice2 minimum pulse width, sr inputs (hp i/o banks only) 0.54 0.54 0.63 0.63 ns, min t rpw_ologice3 minimum pulse width, sr inputs (hr i/o banks only) 0.54 0.54 0.63 0.63 ns, min s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 29 input serializer/deserializer switching characteristics table 26: iserdes switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to cl kdiv 0.01/0.12 0.02/0.13 0.02/0.15 0.02/0.15 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.39/?0.02 0.44/?0.02 0.63/?0.02 0. 63/?0.02 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) ?0.12/0.29 ?0.12/0.31 ?0. 12/0.35 ?0.12/0.35 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk ?0.02/0.11 ?0.02/0.12 ?0. 02/0.15 ?0.02/0.15 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using idelay) (1) ?0.02/0.11 ?0.02/0.12 ?0. 02/0.15 ?0.02/0.15 ns t isdck_d_ddr / t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode ?0.02/0.11 ?0.02/0.12 ?0. 02/0.15 ?0.02/0.15 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using idelay) (1) 0.11/0.11 0.12/0.12 0.15/0.15 0.15/0.15 ns sequential delays t iscko_q clkdiv to out at q pin 0.46 0.47 0.58 0.58 ns propagation delays t isdo_do d input to do output pin 0.09 0.10 0.12 0.12 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in the timing report. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 30 output serializer/deserializer switching characteristics table 27: oserdes switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkd iv 0.37/0.02 0.40/ 0.02 0.55/0.02 0.55/0.02 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0 .49/?0.15 0.56/?0.15 0. 68/?0.15 0.68/?0.15 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.27/?0.15 0.30/?0.15 0. 34/?0.15 0.34/?0.15 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.41 0.46 0.75 0.75 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.01 ns sequential delays t oscko_oq clock to out from clk to oq 0.35 0.37 0.42 0.42 ns t oscko_tq clock to out from clk to tq 0.41 0.43 0.49 0.49 ns combinatorial t osdo_ttq t input to tq out 0.73 0.81 0.97 0.97 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in the timing report. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 31 input/output delay switching characteristics table 28: input/output delay switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m idelayctrl t dlycco_rdy reset to ready for idelayctrl 3.22 3.22 3.22 3.22 s f idelayctrl_ref attribute refclk frequency = 200.0 (1) 200 200 200 200 mhz attribute refclk frequency = 300.0 (1) 300 300 n/a n/a mhz attribute refclk frequency = 400.0 (1) 400 400 n/a n/a mhz idelayctrl_ref_precision refclk precision 10 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 52.00 52.00 52.00 52.00 ns idelay/odelay t idelayresolution idelay/odelay chain delay resolution 1/(32 x 2 x f ref )ps t idelaypat_jit and t odelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (2) 0000ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (3) 5 5 5 5 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (4) 9 9 9 9 ps per tap t idelay_clk_max / t odelay_clk_max maximum frequency of clk input to idelay/odelay 800 800 710 710 mhz t idcck_ce / t idckc_ce ce pin setup/hold with respect to c for idelay 0.11/0.10 0.14/0.12 0.18/0.14 0.18/0.14 ns t odcck_ce / t odckc_ce ce pin setup/hold with respect to c for odelay 0.14/0.03 0.16/0.04 0.19/0.05 0.19/0.05 ns t idcck_inc / t idckc_inc inc pin setup/hold with respect to c for idelay 0.10/0.14 0.12/0.16 0.14/0.20 0.14/0.20 ns t odcck_inc / t odckc_inc inc pin setup/hold with respect to c for odelay 0.10/0.07 0.12/0.08 0.13/0.09 0.13/0.09 ns t idcck_rst / t idckc_rst rst pin setup/hold with respect to c for idelay 0.13/0.08 0.14/0.10 0.16/0.12 0.16/0.12 ns t odcck_rst / t odckc_rst rst pin setup/hold with respect to c for odelay 0.16/0.04 0.19/0.06 0.24/0.08 0.24/0.08 ns t iddo_idatain propagation delay through idelay note 5 note 5 note 5 note 5 ps t oddo_odatain propagation delay through odelay note 5 note 5 note 5 note 5 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps, and at 400 mhz = 39 ps. 2. when high_performance mode is set to true or false. 3. when high_performance mode is set to true. 4. when high_performance mode is set to false. 5. delay depends on idelay/odelay tap setting. see the timing report for actual values. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 32 table 29: io_fifo switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m io_fifo clock to out delays t offcko_do rdclk to q outputs 0.51 0.56 0.63 0.63 ns t cko_flags clock to io_fifo flags 0.59 0.62 0.81 0.81 ns setup/hold t cck_d /t ckc_d d inputs to wrclk 0.43/?0.01 0. 47/?0.01 0.53/?0.01 0.53/0.09 ns t iffcck_wren /t iffckc_wren wren to wrclk 0.39/?0.01 0.43 /?0.01 0.50/?0.01 0.50/?0.01 ns t offcck_rden /t offckc_rden rden to rdclk 0.49/0.01 0.53/ 0.02 0.61/0.02 0.61/0.02 ns minimum pulse width t pwh_io_fifo reset, rdclk, wrclk 0 .81 0.92 1.08 1.08 ns t pwl_io_fifo reset, rdclk, wrclk 0 .81 0.92 1.08 1.08 ns maximum frequency f max rdclk and wrclk 533.05 470.37 400.00 400.00 mhz s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 33 clb switching characteristics table 30: clb switching ch aracteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m combinatorial delays t ilo an ? dn lut address to a 0.05 0.05 0.06 0.06 ns, max t ilo_2 an ? dn lut address to amux/cmux 0.15 0.16 0.19 0.19 ns, max t ilo_3 an ? dn lut address to bmux_a 0.24 0.25 0.30 0.30 ns, max t ito an ? dn inputs to a ? d q outpu ts 0.58 0.61 0.74 0.74 ns, max t axa ax inputs to amux output 0.38 0.40 0.49 0.49 ns, max t axb ax inputs to bmux output 0.40 0.42 0.52 0.52 ns, max t axc ax inputs to cmux output 0.39 0.41 0.50 0.50 ns, max t axd ax inputs to dmux output 0.43 0.44 0.52 0.52 ns, max t bxb bx inputs to bmux output 0.31 0.33 0.40 0.40 ns, max t bxd bx inputs to dmux output 0.38 0.39 0.47 0.47 ns, max t cxc cx inputs to cmux output 0.27 0.28 0.34 0.34 ns, max t cxd cx inputs to dmux output 0.33 0.34 0.41 0.41 ns, max t dxd dx inputs to dmux output 0.32 0.33 0.40 0.40 ns, max sequential delays t cko clock to aq ? dq outputs 0.26 0.27 0.32 0.32 ns, max t shcko clock to amux ? dmux outputs 0.32 0.32 0.39 0.39 ns, max setup and hold times of clb fl ip-flops before/after clock clk t as /t ah a n ?d n input to clk on a ? d flip-flops 0.01/0. 12 0.02/0.13 0.03/0.18 0.03/0.24 ns, min t dick /t ckdi a x ?d x input to clk on a ? d flip-flops 0.04/0. 14 0.04/0.14 0.05/0.20 0.05/0.26 ns, min a x ?d x input through muxs and/or carry logic to clk on a ? d flip-flops 0.36/0.10 0.37/0.11 0.46/ 0.16 0.46/0.22 ns, min t ceck_clb /t ckce_clb ce input to clk on a ? d flip-flops 0.19/ 0.05 0.20/0.05 0.25/0.05 0.25/0.11 ns, min t srck /t cksr sr input to clk on a ? d flip-flops 0.30/ 0.05 0.31/0.07 0.37/0.09 0.37/0.22 ns, min set/reset t srmin sr input minimum pulse width 0.52 0.78 1.04 1.04 ns, min t rq delay from sr input to aq ? dq flip-flops 0.38 0.38 0.46 0.46 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.34 0.35 0.43 0.43 ns, max f tog toggle frequency (for export control) 1818 1818 1818 1818 mhz s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 34 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) table 31: clb distributed ram swit ching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m sequential delays t shcko (1) clock to a ? b outputs 0.68 0.70 0.85 0.85 ns, max t shcko_1 clock to amux ? bmux outputs 0.91 0.95 1.15 1.15 ns, max setup and hold times before/after clock clk t ds_lram /t dh_lram a ? d inputs to clk 0.45/0.23 0.45/ 0.24 0.54/0.27 0. 54/0.28 ns, min t as_lram /t ah_lram address an inputs to clock 0.13/0. 50 0.14/0.50 0.17/0.58 0.17/0.61 ns, min address an inputs through muxs and/or carry logic to clock 0.40/0.16 0.42/0.17 0.52/ 0.23 0.52/0.29 ns, min t ws_lram /t wh_lram we input to clock 0.29/0.09 0. 30/0.09 0.36/0.09 0. 36/0.11 ns, min t ceck_lram /t ckce_lram ce input to clk 0.29/0.09 0.30/ 0.09 0.37/0.09 0. 37/0.11 ns, min clock clk t mpw minimum pulse width 0.68 0.77 0.91 0.91 ns, min t mcp minimum clock period 1.35 1.54 1.82 1.82 ns, min notes: 1. t shcko also represents the clk to xmux output. refer to the timing report for the clk to xmux path. table 32: clb shift register switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m sequential delays t reg clock to a ? d outputs 0.96 0.98 1.20 1.20 ns, max t reg_mux clock to amux ? dmux output 1.19 1.23 1.50 1.50 ns, max t reg_m31 clock to dmux output via m31 output 0.89 0.91 1.10 1.10 ns, max setup and hold times before/after clock clk t ws_shfreg /t wh_shfreg we input 0.26/0.09 0.27/0.09 0 .33/0.09 0.33/0.11 ns, min t ceck_shfreg /t ckce_shfreg ce input to clk 0.27/0.09 0.28 /0.09 0.33/0.09 0.33/0.11 ns, min t ds_shfreg /t dh_shfreg a ? d inputs to clk 0.28/0.26 0.28 /0.26 0.33/0.30 0.33/0.36 ns, min clock clk t mpw_shfreg minimum pulse width 0.55 0.65 0.78 0.78 ns, min s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 35 block ram and fifo switching characteristics table 33: block ram and fifo switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg (1) clock clk to dout out put (without output register) (2)(3) 1.57 1.80 2.08 2.08 ns, max clock clk to dout output (with output register) (4)(5) 0.54 0.63 0.75 0.75 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without outpu t register) (2)(3) 2.35 2.58 3.26 3.26 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.62 0.69 0.80 0.80 ns, max t rcko_do_cascout and t rcko_do_cascout_reg clock clk to dout output with cascade (without outpu t register) (2) 2.21 2.45 2.80 2.80 ns, max clock clk to dout output with cascade (with output register) (4) 0.98 1.08 1.24 1.24 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.65 0.74 0.89 0.89 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 0.79 0.87 0.98 0.98 ns, max t rcko_parity_ecc clock clk to eccparit y in ecc encode only mode 0.66 0.72 0.80 0.80 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (without output register) 2.17 2.38 3.01 3.01 ns, max clock clk to biterr (with output register) 0.57 0.65 0.76 0.76 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without outpu t register) 0.64 0.74 0.90 0.90 ns, max clock clk to rdaddr output with ecc (with output register) 0.71 0.79 0.92 0.92 ns, max setup and hold times before/after clock clk t rcck_addra /t rckc_addra addr inputs (8) 0.38/0.27 0.42/0.28 0.48/0 .31 0.48/0.38 ns, min t rdck_di_wf_nc / t rckd_di_wf_nc data input setup/hold time when block ram is configured in write_first or no_change mode (9) 0.49/0.51 0.55/0.53 0.63/0 .57 0.63/0.57 ns, min t rdck_di_rf /t rckd_di_rf data input setup/hold time when block ram is configured in read_first mode (9) 0.17/0.25 0.19/0.29 0.21/0 .35 0.21/0.35 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.42/0.37 0.47/0.39 0.53/0 .43 0.53/0.58 ns, min t rdck_di_eccw /t rckd_di_eccw din inputs with block ram ecc encode only (9) 0.79/0.37 0.87/0.39 0.99/0 .43 0.99/0.58 ns, min t rdck_di_ecc_fifo / t rckd_di_ecc_fifo din inputs with fifo ecc in standard mode (9) 0.89/0.47 0.98/0.50 1.12/0 .54 1.12/0.69 ns, min t rcck_injectbiterr / t rckc_injectbiterr inject single/double bit error in ecc mode 0.49/0.30 0.55/0.31 0.63/0 .34 0.63/0.43 ns, min t rcck_en /t rckc_en block ram enable (en) input 0.30/0. 17 0.33/0.18 0.38/0.20 0.38/0.32 ns, min t rcck_regce /t rckc_regce ce input of output re gister 0.21/0.13 0. 25/0.13 0.31/0.14 0.31/0.19 ns, min t rcck_rstreg /t rckc_rstreg synchronous rstreg i nput 0.25/0.06 0.27/0. 06 0.29/0.06 0.29/0.14 ns, min t rcck_rstram /t rckc_rstram synchronous rstram input 0.27/0.35 0.29/0.37 0.31/0.39 0.31/0.39 ns, min t rcck_wea /t rckc_wea write enable (we) input (block ram only) 0 .38/0.15 0.41/0.16 0.46/0 .17 0.46/0.29 ns, min s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 36 t rcck_wren /t rckc_wren wren fifo inputs 0.39/0.25 0.39/ 0.30 0.40/0.37 0.40/0.49 ns, min t rcck_rden /t rckc_rden rden fifo inputs 0.36/ 0.26 0.36/0.30 0.37/0.37 0.37/0.49 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (10) 0.76 0.83 0.93 0.93 ns, max t rrec_rst /t rrem_rst fifo reset recovery and removal timing (11) 1.59/?0.68 1.76/?0.68 2.01/ ?0.68 2.01/?0.68 ns, max maximum frequency f max_bram_wf_nc block ram (write first and no change modes) when not in sdp rf mode 601.32 543.77 458.09 458.09 mhz f max_bram_rf_performance block ram (read first, performance mode) when in sdp rf mode but no address overlap between port a and port b 601.32 543.77 458.09 458.09 mhz f max_bram_rf_delayed_write block ram (read first, delayed_write mode) when in sdp rf mode and there is possibility of overlap between port a and port b addresses 528.26 477.33 400.80 400.80 mhz f max_cas_wf_nc block ram cascade (write first, no change mode) when cascade but not in rf mode 551.27 493.83 408.00 408.00 mhz f max_cas_rf_performance block ram cascade (read first, performance mode) when in cascade with rf mode and no possibility of address overlap/one port is disabled 551.27 493.83 408.00 408.00 mhz f max_cas_rf_delayed_write when in cascade rf mode and there is a possibility of address overlap between port a and port b 478.24 427.35 350.88 350.88 mhz f max_fifo fifo in all modes without ecc 601.32 543.77 458.09 458.09 mhz f max_ecc block ram and fifo in ecc confi guration 484.26 430.85 351.12 351.12 mhz notes: 1. the timing report shows all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted) . otherwise, block ram data corruption is possible. 9. these parameters include both a and b inputs as well as the parity inputs of a and b. 10. t rco_flags includes the following flags: aempty, afull, empty, full, rderr, wrerr, rdcount, and wrcount. 11. rden and wren must be held low prior to and during reset. the fifo reset must be asserted for at least five positive clock e dges of the slowest clock (wrclk or rdclk). table 33: block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 37 dsp48e1 switching characteristics table 34: dsp48e1 switching characteristics symbol description speed grade units -3 -2/-2l/-2g -1 -1m setup and hold times of data/control pins to the inpu t register clock t dspdck_a_areg /t dspckd_a_areg a input to a register clk 0.24/0. 12 0.27/0.14 0.31/ 0.16 0.33/0.18 ns t dspdck_b_breg /t dspckd_b_breg b input to b register clk 0.28/0. 13 0.32/0.14 0.39/ 0.15 0.41/0.18 ns t dspdck_c_creg /t dspckd_c_creg c input to c register clk 0.15/0. 15 0.17/0.17 0.20/ 0.20 0.20/0.22 ns t dspdck_d_dreg /t dspckd_d_dreg d input to d register clk 0.21/0. 19 0.27/0.22 0.35/ 0.26 0.35/0.27 ns t dspdck_acin_areg /t dspckd_acin_areg acin input to a register clk 0.2 1/0.12 0.24/0.14 0.2 7/0.16 0.30/0.16 ns t dspdck_bcin_breg /t dspckd_bcin_breg bcin input to b register clk 0.2 2/0.13 0.25/0.14 0.3 0/0.15 0.32/0.15 ns setup and hold times of data pins to the pipeline register clock t dspdck_ { a, b } _mreg_mult / t dspckd_ { a, b } _mreg_mult {a, b} input to m register clk using multiplier 2.04/?0.01 2.34/?0.01 2. 79/?0.01 2.79/?0.01 ns t dspdck_ { a, d } _adreg / t dspckd_ { a, d } _adreg {a, d} input to ad register clk 1. 09/?0.02 1.25/?0.02 1.49/ ?0.02 1.49/?0.02 ns setup and hold times of data/control pins to the output register clock t dspdck_{a, b}_preg_mult / t dspckd_{a, b} _preg_mult {a, b,} input to p register clk using multiplier 3.41/?0.24 3.90/?0.24 4. 64/?0.24 4.64/?0.24 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk using multiplier 3.33/?0.62 3.81/?0.62 4. 53/?0.62 4.53/?0.62 ns t dspdck_{a, b} _preg / t dspckd_{a, b} _preg a or b input to p register clk not using multiplier 1.47/?0.24 1.68/?0.24 2. 00/?0.24 2.00/?0.24 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk not using multiplier 1.30/?0.22 1.49/?0.22 1. 78/?0.22 1.78/?0.22 ns t dspdck_pcin_preg / t dspckd_pcin_preg pcin input to p register clk 1.12/?0 .13 1.28/?0.13 1.52/?0.13 1.52/?0.13 ns setup and hold times of the ce pins t dspdck_{cea;ceb}_{areg;breg} / t dspckd_{cea;ceb}_{areg;breg} {cea; ceb} input to {a; b} register clk 0.30/0.05 0.36/0.06 0.44/0.09 0.44/0.09 ns t dspdck_cec_creg /t dspckd_cec_creg cec input to c register clk 0.24/ 0.08 0.29/0.09 0.3 6/0.11 0.36/0.11 ns t dspdck_ced_dreg /t dspckd_ced_dreg ced input to d register clk 0.31/?0 .02 0.36/?0.02 0.44/ ?0.02 0.44/0.02 ns t dspdck_cem_mreg /t dspckd_cem_mreg cem input to m register clk 0.26/ 0.15 0.29/0.17 0.3 3/0.20 0.33/0.20 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.31/ 0.01 0.36/0.01 0.4 5/0.01 0.45/0.01 ns setup and hold times of the rst pins t dspdck_{rsta; rstb}_{areg; breg} / t dspckd_{rsta; rstb}_{areg; breg} {rsta, rstb} input to {a, b} register clk 0.34/0.10 0.39/0.11 0.47/0.13 0.47/0.14 ns t dspdck_rstc_creg /t dspckd_rstc_creg rstc input to c register clk 0.06/ 0.22 0.07/0.24 0.0 8/0.26 0.08/0.26 ns t dspdck_rstd_dreg /t dspckd_rstd_dreg rstd input to d register clk 0.37/ 0.06 0.42/0.06 0.5 0/0.07 0.50/0.07 ns t dspdck_rstm_mreg /t dspckd_rstm_mreg rstm input to m register clk 0.18/ 0.18 0.20/0.21 0.2 3/0.24 0.23/0.24 ns t dspdck_rstp_preg /t dspckd_rstp_preg rstp input to p register clk 0.24/ 0.01 0.26/0.01 0.3 0/0.01 0.30/0.11 ns combinatorial delays from input pins to output pins t dspdo_a_carryout_mult a input to carryout output using multiplier 3.21 3.69 4.39 4.39 ns t dspdo_d_p_mult d input to p output using multiplier 3.15 3.61 4.30 4.30 ns s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 38 t dspdo_a_p a input to p output not using multiplier 1.30 1.48 1.76 1.76 ns t dspdo_c_p c input to p output 1.13 1.30 1.55 1.55 ns combinatorial delays from input pins to cascading output pins t dspdo_{a; b}_{acout; bcout} {a, b} input to {acout, bcout} output 0.47 0.53 0.63 0.63 ns t dspdo_{a, b}_car rycascout_mult {a, b} input to carrycascout output using multiplier 3.44 3.94 4.69 4.69 ns t dspdo_d_carrycascout_mult d input to carrycascout output using multiplier 3.36 3.85 4.58 4.58 ns t dspdo_{a, b}_c arrycascout {a, b} input to carrycascout output not using multiplier 1.50 1.72 2.04 2.04 ns t dspdo_c_ca rrycascout c input to carrycascout output 1.34 1.53 1.83 1.83 ns combinatorial delays from cascading input pins to all output pins t dspdo_acin_p_mult acin input to p output using multiplier 3.09 3.55 4.24 4.24 ns t dspdo_acin_p acin input to p output not using multiplier 1.16 1.33 1.59 1.59 ns t dspdo_acin_acout acin input to acout output 0.32 0.37 0.45 0.45 ns t dspdo_acin_car rycascout_mult acin input to carrycascout output using multiplier 3.30 3.79 4.52 4.52 ns t dspdo_acin_carrycascout acin input to carrycascout output not using multiplier 1.37 1.57 1.87 1.87 ns t dspdo_pcin_p pcin input to p output 0.94 1.08 1.29 1.29 ns t dspdo_pcin_carrycascout pcin input to carrycascout output 1.15 1.32 1.57 1.57 ns clock to outs from output re gister clock to output pins t dspcko_p_preg clk preg to p output 0.33 0.35 0.39 0.39 ns t dspcko_carry cascout_preg clk preg to carrycascout output 0.44 0.50 0.59 0.59 ns clock to outs from pipeline register clock to output pins t dspcko_p_mreg clk mreg to p output 1.42 1.64 1.96 1.96 ns t dspcko_carry cascout_mreg clk mreg to carrycascout output 1.63 1.87 2.24 2.24 ns t dspcko_p_adreg_mult clk adreg to p output using multiplier 2.30 2.63 3.13 3.13 ns t dspcko_carrycasc out_adreg_mult clk adreg to carrycascout output using multiplier 2.51 2.87 3.41 3.41 ns table 34: dsp48e1 switching characteristics (cont?d) symbol description speed grade units -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 39 clock to outs from input re gister clock to output pins t dspcko_p_areg_mult clk areg to p output using multiplier 3.34 3.83 4.55 4.55 ns t dspcko_p_breg clk breg to p output not using multiplier 1.39 1.59 1.88 1.88 ns t dspcko_p_creg clk creg to p output not using multiplier 1.43 1.64 1.95 1.95 ns t dspcko_p_dreg_mult clk dreg to p output using multiplier 3.32 3.80 4.51 4.51 ns clock to outs from input register clock to cascad ing output pins t dspcko_{acout; bc out}_{areg; breg} clk (acout, bcout) to {a,b} register output 0.55 0.62 0.74 0.74 ns t dspcko_carrycascout_ {areg, breg}_mult clk (areg, breg) to carrycascout output using multiplier 3.55 4.06 4.84 4.84 ns t dspcko_carrycascout_ breg clk (breg) to carrycascout output not using multiplier 1.60 1.82 2.16 2.16 ns t dspcko_carrycasc out_ dreg_mult clk (dreg) to carrycascout output using multiplier 3.52 4.03 4.79 4.79 ns t dspcko_carryc ascout_ creg clk (creg) to carrycascout output 1.64 1.88 2.23 2.23 ns maximum frequency f max with all registers used 741.84 650.20 547.95 547.95 mhz f max_patdet with pattern detector 627.35 549.75 463.61 463.61 mhz f max_mult_nomreg two register multiply without mreg 412.20 360.75 303.77 303.77 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 374.25 327.65 276.01 276.01 mhz f max_preadd_mult_noadreg without adreg 468.82 408.66 342.70 342.70 mhz f max_preadd_mult_ noadreg_patdet without adreg with pattern detect 468.82 408.66 342.70 342.70 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 306.84 267.81 225.02 225.02 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 285.23 249.13 209.38 209.38 mhz table 34: dsp48e1 switching characteristics (cont?d) symbol description speed grade units -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 40 clock buffers and networks table 35: global clock switching charac teristics (including bufgctrl) symbol description speed grade units -3 -2/-2l/-2g -1 -1m t bccck_ce /t bcckc_ce (1) ce pins setup/hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 ns t bccck_s /t bcckc_s (1) s pins setup/hold 0.12/0.30 0. 14/0.38 0.26/0.38 0.26/0.92 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.08 0.10 0.12 0.12 ns maximum frequency f max_bufg global clock tree (bufg) 741.00 710.00 625.00 625.00 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux primitive that assures glitch-free operation. the other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matc hes on a cycle-for-cycle basis when switchin g between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. table 36: input/output clock switching characteristics (bufio) symbol description speed grade units -3 -2/-2l/-2g -1 -1m t biocko_o clock to out delay from i to o 1.04 1.14 1.32 1.32 ns maximum frequency f max_bufio i/o clock tree (bufio) 800.00 800.00 710.00 710.00 mhz table 37: regional clock buffer swit ching characteristics (bufr) symbol description speed grade units -3 -2/-2l/-2g -1 -1m t brcko_o clock to out delay from i to o 0.60 0.65 0.77 0.77 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.30 0.32 0.38 0.38 ns t brdo_o propagation delay from clr to o 0.71 0.75 0.96 0.96 ns maximum frequency f max_bufr (1) regional clock tree (bufr) 600.00 540.00 450.00 450.00 mhz notes: 1. the maximum input frequency to the bufr and bufmr is the bufio f max frequency. table 38: horizontal clock buffer swit ching characteristics (bufh) symbol description speed grade units -3 -2/-2l/-2g -1 -1m t bhcko_o bufh delay from i to o 0.10 0.11 0.13 0.13 ns t bhcck_ce /t bhckc_ce ce pin setup and hold 0.20/0.16 0.23/0.20 0.38/0.21 0.38/0.79 ns maximum frequency f max_bufh horizontal clock buffer (buf h) 741.00 710.00 625.00 625.00 mhz s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 41 mmcm switching characteristics table 39: duty cycle distortion and clock tree skew symbol description device speed grade units -3 -2g -2 -2l -1 -1m t dcd_clk global clock tree duty cycle distortion (1) all 0.200.200.200.200.200.20 ns t ckskew global clock tree skew (2) xc7v585t 0.75 n/a 0.91 0.91 0.98 n/a ns xc7v2000t n/a 0.39 0.39 0.39 0.39 n/a ns xc7vx330t 0.60 n/a 0.74 0.74 0.79 n/a ns xc7vx415t 0.76 n/a 0.84 0.84 0.91 n/a ns xc7vx485t 0.60 n/a 0.74 0.74 0.79 n/a ns xc7vx550t 0.73 n/a 0.88 0.88 0.96 n/a ns xc7vx690t 0.73 n/a 0.88 0.88 0.96 n/a ns XC7VX980T n/a n/a 0.91 0.91 0.98 n/a ns xc7vx1140t n/a 0.390.390.390.39 n/a ns xq7v585t n/a n/a 0.91 0.91 0.98 0.98 ns xq7vx330t n/a n/a 0.74 0.74 0.79 0.79 ns xq7vx485t n/a n/a 0.74 0.74 0.79 0.79 ns xq7vx690t n/a n/a 0.88 n/a 0.96 n/a ns xq7vx980t n/a n/a n/a 0.91 0.98 n/a ns t dcd_bufio i/o clock tree duty cycle distortion all 0.12 0.12 0.12 0.12 0.12 0.12 ns t bufioskew i/o clock tree skew across one clock region all 0.02 0.02 0.02 0.02 0.02 0.02 ns t dcd_bufr regional clock tree duty cycle distor tion all 0.15 0.15 0.15 0.15 0.15 0.15 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the i/o flip-flops. for all i/o standards, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements in a single slr. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx timing analyzer tools to evaluate clock skew specific to your application. table 40: mmcm specification symbol description speed grade units -3 -2/-2l/-2g -1 -1m mmcm_f inmax maximum input clock frequency 1066.00 933.00 800.00 800.00 mhz mmcm_f inmin minimum input clock frequency 10 10 10 10 mhz mmcm_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max mmcm_f induty allowable input duty cycle: 10?49 mhz 25 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 45 % mmcm_f min_psclk minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase shift clock frequency 550.00 500.00 450.00 450.00 mhz mmcm_f vcomin minimum mmcm vco frequency 600.00 600.00 600.00 600.00 mhz mmcm_f vcomax maximum mmcm vco frequency 1600.00 1440.00 1200.00 1200.00 mhz s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 42 mmcm_f bandwidth low mmcm bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs (2) 0.12 0.12 0.12 0.12 ns mmcm_t outjitter mmcm output jitter note 3 mmcm_t outduty mmcm output clock duty cycle precision (4) 0.20 0.20 0.20 0.20 ns mmcm_t lockmax mmcm maximum lock time 100 100 100 100 s mmcm_f outmax mmcm maximum output frequency 1066.00 933.00 800.00 800.00 mhz mmcm_f outmin mmcm minimum output frequency (5)(6) 4.69 4.69 4.69 4.69 mhz mmcm_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max mmcm_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector 10.00 10.00 10.00 10.00 mhz mmcm_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle mmcm switching characteristics setup and hold t mmcmdck_psen / t mmcmckd_psen setup and hold of phase-shift enable 1 .04/0.00 1.04/0.00 1. 04/0.00 1.04/0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase-shift increment/decrement 1.04/0.00 1.04/0.00 1. 04/0.00 1.04/0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone 0.59 0.68 0.81 0.81 ns dynamic reconfiguration port (drp ) for mmcm before and after dclk t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_di / t mmcmckd_di di setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_den / t mmcmckd_den den setup/hold 1.76/0. 00 1.97/0.00 2.29/0.00 2.29/0.00 ns, min t mmcmdck_dwe / t mmcmckd_dwe dwe setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 mhz, max notes: 1. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.c om/products/intell ectual-property/cl ocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when clkout4_cascade = true, mmcm_f outmin is 0.036 mhz. table 40: mmcm specification (cont?d) symbol description speed grade units -3 -2/-2l/-2g -1 -1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 43 pll switching characteristics table 41: pll specification symbol description speed grade units -3 -2/-2l/-2g -1 -1m pll_f inmax maximum input clock frequency 1066.00 933.00 800.00 800.00 mhz pll_f inmin minimum input clock frequency 19.00 19.00 19.00 19.00 mhz pll_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max pll_f induty allowable input duty cycle: 19?49 mhz 25 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 45 % pll_f vcomin minimum pll vco frequency 800.00 800.00 800.00 800.00 mhz pll_f vcomax maximum pll vco frequency 2133.00 1866.00 1600.00 1600.00 mhz pll_f bandwidth low pll bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high pll bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz pll_t statphaoffset static phase offset of the pll outputs (2) 0.12 0.12 0.12 0.12 ns pll_t outjitter pll output jitter note 3 pll_t outduty pll output clock duty cycle precision (4) 0.20 0.20 0.20 0.20 ns pll_t lockmax pll maximum lock time 100 100 100 100 s pll_f outmax pll maximum output frequency 10 66.00 933.00 800.00 800.00 mhz pll_f outmin pll minimum output frequency (5) 6.25 6.25 6.25 6.25 mhz pll_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max pll_rst minpulse minimum reset pulse wi dth 5.00 5.00 5.00 5.00 ns pll_f pfdmax maximum frequency at the phase frequen cy detector 550.00 500.00 450.00 450.00 mhz pll_f pfdmin minimum frequency at the phase frequency detector 19.00 19.00 19.00 19.00 mhz pll_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle dynamic reconfiguration port (drp ) for pll before and after dclk t plldck_daddr / t pllckd_daddr daddr setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63 /0.15 ns, min t plldck_di / t pllckd_di di setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63 /0.15 ns, min t plldck_den / t pllckd_den den setup/hold 1.76/0.00 1.97/0.0 0 2.29/0.00 2.29 /0.00 ns, min t plldck_dwe / t pllckd_dwe dwe setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63 /0.15 ns, min t pllcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 mhz, max notes: 1. the pll does not filter typical spread-spectrum input clocks bec ause they are usually far below the bandwidth filter frequenc ies. 2. the static offset is measured between any pll outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 44 device pin-to-pin output parameter guidelines table 42: clock-capable clock input to output de lay without mmcm/pll (near clock region) (1) symbol description device speed grade units -3 -2g -2 -2l -1 -1m sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, without mmcm/pll. t ickof clock-capable clock input and outff at pins/banks closest to the bufgs without mmcm/pll (near clock region) (2) xc7v585t 5.63 n/a 6.20 6.20 6.97 n/a ns xc7v2000t n/a 5.66 5.66 5.66 6.35 n/a ns xc7vx330t 5.41 n/a 5.97 5.97 6.71 n/a ns xc7vx415t 5.46 n/a 5.96 5.96 6.70 n/a ns xc7vx485t 5.29 n/a 5.84 5.84 6.57 n/a ns xc7vx550t 5.45 n/a 6.02 6.02 6.76 n/a ns xc7vx690t 5.46 n/a 6.02 6.02 6.76 n/a ns XC7VX980T n/a n/a 6.12 6.12 6.87 n/a ns xc7vx1140t n/a 5.59 5.59 5.59 6.28 n/a ns xq7v585t n/a n/a 6.20 6.20 6.97 6.97 ns xq7vx330t n/a n/a 5.97 5.97 6.71 6.71 ns xq7vx485t n/a n/a 5.84 5.84 6.57 6.57 ns xq7vx690t n/a n/a 6.02 n/a 6.76 n/a ns xq7vx980t n/a n/a n/a 6.12 6.87 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net in a single slr. 2. refer to the die level bank numbering overview section of 7 series fpga packaging and pinout specification ( ug475 ). s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 45 table 43: clock-capable clock input to output de lay without mmcm/pll (far clock region) (1) symbol description device speed grade units -3 -2g -2 -2l -1 -1m sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, without mmcm/pll. t ickoffar clock-capable clock input and outff at pins/banks farthest from the bufgs without mmcm/pll (far clock region) (2) xc7v585t 6.81 n/a 7.53 7.53 8.44 n/a ns xc7v2000t n/a 6.00 6.00 6.00 6.73 n/a ns xc7vx330t 6.31 n/a 6.97 6.97 7.83 n/a ns xc7vx415t 6.36 n/a 6.90 6.90 7.69 n/a ns xc7vx485t 6.20 n/a 6.86 6.86 7.69 n/a ns xc7vx550t 6.66 n/a 7.37 7.37 8.27 n/a ns xc7vx690t 6.69 n/a 7.37 7.37 8.27 n/a ns XC7VX980T n/a n/a 7.47 7.47 8.37 n/a ns xc7vx1140t n/a 5.93 5.93 5.93 6.65 n/a ns xq7v585t n/a n/a 7.53 7.53 8.44 8.44 ns xq7vx330t n/a n/a 6.97 6.97 7.83 7.83 ns xq7vx485t n/a n/a 6.86 6.86 7.69 7.69 ns xq7vx690t n/a n/a 7.37 n/a 8.27 n/a ns xq7vx980t n/a n/a n/a 7.47 8.37 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net in a single slr. 2. refer to the die level bank numbering overview section of 7 series fpga packaging and pinout specification ( ug475 ). s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 46 table 44: clock-capable clock input to output delay with mmcm symbol description device speed grade units -3 -2g -2 -2l -1 -1m sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc7v585t 1.07 n/a 1.07 1.07 1.07 n/a ns xc7v2000t n/a 0.82 0.82 0.82 0.82 n/a ns xc7vx330t 1.01 n/a 1.01 1.01 1.01 n/a ns xc7vx415t 1.07 n/a 1.07 1.07 1.07 n/a ns xc7vx485t 0.91 n/a 0.91 0.91 0.91 n/a ns xc7vx550t 0.97 n/a 0.97 0.97 0.97 n/a ns xc7vx690t 1.07 n/a 1.07 1.07 1.07 n/a ns XC7VX980T n/a n/a 0.96 0.96 0.96 n/a ns xc7vx1140t n/a 0.82 0.82 0.82 0.82 n/a ns xq7v585t n/a n/a 1.07 1.07 1.07 1.07 ns xq7vx330t n/a n/a 1.01 1.01 1.01 1.01 ns xq7vx485t n/a n/a 0.91 0.91 0.91 0.91 ns xq7vx690t n/a n/a 1.07 n/a 1.07 n/a ns xq7vx980t n/a n/a n/a 0.96 0.96 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net in a single slr. 2. mmcm output jitter is already included in the timing calculation. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 47 table 45: clock-capable clock input to output delay with pll symbol description device speed grade units -3 -2g -2 -2l -1 -1m sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, with pll. t ickofpllcc clock-capable clock input and outff with pll xc7v585t 0.96 n/a 0.96 0.96 0.96 n/a ns xc7v2000t n/a 0.71 0.71 0.71 0.71 n/a ns xc7vx330t 0.90 n/a 0.90 0.90 0.90 n/a ns xc7vx415t 0.96 n/a 0.96 0.96 0.96 n/a ns xc7vx485t 0.80 n/a 0.80 0.80 0.80 n/a ns xc7vx550t 0.86 n/a 0.86 0.86 0.86 n/a ns xc7vx690t 0.96 n/a 0.96 0.96 0.96 n/a ns XC7VX980T n/a n/a 0.85 0.85 0.85 n/a ns xc7vx1140t n/a 0.71 0.71 0.71 0.71 n/a ns xq7v585t n/a n/a 0.96 0.96 0.96 0.96 ns xq7vx330t n/a n/a 0.90 0.90 0.90 0.90 ns xq7vx485t n/a n/a 0.80 0.80 0.80 0.80 ns xq7vx690t n/a n/a 0.96 n/a 0.96 n/a ns xq7vx980t n/a n/a n/a 0.85 0.85 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net in a single slr. 2. pll output jitter is already included in the timing calculation. table 46: pin-to-pin, clock-to-out using bufio symbol description speed grade units -3 -2/-2l/-2g -1 -1m sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, with bufio. t ickofcs clock-to-out of i/o clock for hr i/o banks 4.93 5.52 6.20 6.20 ns clock-to-out of i/o clock for hp i/o banks 4.85 5.44 6.11 6.11 ns s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 48 device pin-to-pin input parameter guidelines table 47: global clock input setup and hold without mmcm/ pll with zhold_delay on hr i/o banks (only) symbol description device speed grade units -3 -2g -2 -2l -1 -1m input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psfd /t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm/pll with zhold_delay on hr i/o banks xc7v585t 3.12/?0.37 n/a 3.19/?0.3 7 3.19/?0.37 3.42/?0.37 n/a ns xc7v2000t n/a n/a n/a n/a n/a n/a ns xc7vx330t 2.90/?0.31 n/a 2.96/?0 .31 2.96/?0.31 3.16/?0.31 n/a ns xc7vx415t n/a n/a n/a n/a n/a n/a ns xc7vx485t n/a n/a n/a n/a n/a n/a ns xc7vx550t n/a n/a n/a n/a n/a n/a ns xc7vx690t n/a n/a n/a n/a n/a n/a ns XC7VX980T n/a n/a n/a n/a n/a n/a ns xc7vx1140t n/a n/a n/a n/a n/a n/a ns xq7v585t n/a n/a 3.19/?0.37 3.19/?0 .37 3.42/?0.37 3.42/?0.37 ns xq7vx330t n/a n/a 2.96/?0.31 2.96/ ?0.31 3.16/?0.31 3.16/?0.31 ns xq7vx485t n/a n/a n/a n/a n/a n/a ns xq7vx690t n/a n/a n/a n/a n/a n/a ns xq7vx980t n/a n/a n/a n/a n/a n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 49 table 48: clock-capable clock input setup and hold with mmcm symbol description device speed grade units -3 -2g -2 -2l -1 -1m input setup and hold time relative to global clock input signal for sstl15 standard. (1)(2) t psmmcmcc / t phmmcmcc no delay clock-capable clock input and iff (3) with mmcm xc7v585t 2.71/?0.10 n/a 3 .00/?0.10 3.00/?0.1 0 3.33/?0.10 n/a ns xc7v2000t n/a 2.60/?0.24 2.60/?0.2 4 2.60/?0.24 2.87/?0.24 n/a ns xc7vx330t 2.58/?0.15 n/ a 2.87/?0.15 2.87/?0 .15 3.18/?0.15 n/a ns xc7vx415t 2.73/0.01 n/a 3.03/0 .01 3.03/0.01 3.36/0.01 n/a ns xc7vx485t 2.58/?0.15 n/ a 2.87/?0.15 2.87/?0 .15 3.18/?0.15 n/a ns xc7vx550t 2.72/?0.09 n/ a 3.01/?0.09 3.01/?0 .09 3.34/?0.09 n/a ns xc7vx690t 2.72/0.01 n/a 3.01/0 .01 3.01/0.01 3.34/0.01 n/a ns XC7VX980T n/a n/a 3.00/?0.10 3 .00/?0.10 3.33/?0.10 n/a ns xc7vx1140t n/a 2.61/?0.24 2.61/?0.2 4 2.61/?0.24 2.88/?0.24 n/a ns xq7v585t n/a n/a 3.00/?0.10 3.00/ ?0.10 3.33/?0.10 3.33/?0.10 ns xq7vx330t n/a n/a 2.87/?0.15 2.87/ ?0.15 3.18/?0.15 3.18/?0.15 ns xq7vx485t n/a n/a 2.87/?0.15 2.87/ ?0.15 3.18/?0.15 3.18/?0.15 ns xq7vx690t n/a n/a 3.01/0. 01 n/a 3.34/0.01 n/a ns xq7vx980t n/a n/a n/a 3.00/?0.10 3.33/?0.10 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. listed below are representative values where one global cloc k input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net in a single slr. 3. iff = input flip-flop or latch 4. use ibis to determine any duty-cycle di stortion incurred using various standards. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 50 table 49: clock-capable clock input setup and hold with pll symbol description device speed grade units -3 -2g -2 -2l -1 -1m input setup and hold time relative to clock-capable clock input signal for sstl15 standard. (1)(2) t pspllcc / t phpllcc no delay clock-capable clock input and iff (3) with pll xc7v585t 3.07/?0.21 n/a 3.40/?0. 21 3.40/?0.21 3.72/?0.21 n/a ns xc7v2000t n/a 2.99/?0. 35 2.99/?0.35 2. 99/?0.35 3.27/?0.35 n/a ns xc7vx330t 2.94/?0.26 n/ a 3.26/?0.26 3.26/?0.26 3.57/?0.26 n/a ns xc7vx415t 3.09/?0.10 n/ a 3.42/?0.10 3.42/?0.10 3.75/?0.10 n/a ns xc7vx485t 2.95/?0.26 n/ a 3.26/?0.26 3.26/?0.26 3.58/?0.26 n/a ns xc7vx550t 3.08/?0.20 n/ a 3.40/?0.20 3.40/?0.20 3.74/?0.20 n/a ns xc7vx690t 3.08/?0.10 n/ a 3.40/?0.10 3.40/?0.10 3.74/?0.10 n/a ns XC7VX980T n/a n/a 3.39/?0.21 3. 39/?0.21 3.72/?0.21 n/a ns xc7vx1140t n/a 3.00/?0.35 3.00/?0. 35 3.00/?0.35 3.27/?0.35 n/a ns xq7v585t n/a n/a 3.40/?0.21 3.40/ ?0.21 3.72/?0.21 3.72/?0.21 ns xq7vx330t n/a n/a 3.26/?0.26 3.26/ ?0.26 3.57/?0.26 3.57/?0.26 ns xq7vx485t n/a n/a 3.26/?0.26 3.26/ ?0.26 3.58/?0.26 3.58/?0.26 ns xq7vx690t n/a n/a 3.40/?0. 10 n/a 3.74/?0.10 n/a ns xq7vx980t n/a n/a n/a 3.39/ ?0.21 3.72/?0.21 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. listed below are representative values where one global cloc k input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net in a single slr. 3. iff = input flip-flop or latch 4. use ibis to determine any duty-cycle di stortion incurred using various standards. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 51 table 50: data input setup and hold times relative to a forwarded clock input pin using bufio symbol description speed grade units -3 -2/-2l/-2g -1 -1m input setup and hold time relative to a forwarded clock input pin using bufio for sstl15 standard. t pscs /t phcs setup/hold of i/o clock for hr i/o banks ?0.36/1.36 ?0.36/1.50 ?0.36/1.70 ?0.36/1.70 ns setup/hold of i/o clock for hp i/o banks ?0.34/1.39 ?0.34/1.53 ?0. 34/1.73 ?0.34/1.73 ns table 51: sample window symbol description speed grade units -3 -2/-2l/-2g -1 -1m t samp sampling error at receiver pins (1) 0.51 0.56 0.61 0.61 ns t samp_bufio sampling error at receiver pins using bufio (2) 0.30 0.35 0.40 0.40 ns notes: 1. this parameter indicates the total sampling error of the virtex-7 t and xt fpgas ddr input registers, measured across voltage, temperature, and process. the characterization methodology uses the mmcm to capture the ddr input registers? edges of operation . these measurements include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of the virtex-7 t and xt fpgas ddr input registers, measured across voltage, temperature, and process. the characterization methodology uses the bufio clock network and idelay to capture the ddr input reg isters? edges of operation. these measurements do not include package or clock tree skew. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 52 additional package parameter guidelines the parameters in this section provide the necessary values for calculating timing budgets for virtex-7 t and xt fpga clock transmitter and receiver data-valid windows. table 52: package skew symbol description device package value units t pkgskew package skew (1) xc7v585t ffg1157 232 ps ffg1761 255 ps xc7v2000t fhg1761 308 ps flg1925 266 ps xc7vx330t ffg1157/ffv1157 170 ps ffg1761/ffv1761 270 ps xc7vx415t ffg1157/ffv1157 203 ps ffg1158/ffv1158 237 ps ffg1927/ffv1927 183 ps xc7vx485t ffg1157 191 ps ffg1158 209 ps ffg1761 274 ps ffg1927 209 ps ffg1930 304 ps xc7vx550t ffg1158 217 ps ffg1927 254 ps xc7vx690t ffg1157 239 ps ffg1158 217 ps ffg1761 284 ps ffg1926 238 ps ffg1927 254 ps ffg1930 287 ps XC7VX980T ffg1926 242 ps ffg1928 199 ps ffg1930 243 ps xc7vx1140t flg1926 271 ps flg1928 216 ps flg1930 279 ps xq7v585t rf1157 232 ps rf1761 255 ps xq7vx330t rf1157 170 ps rf1761 270 ps xq7vx485t rf1761 274 ps rf1930 304 ps s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 53 t pkgskew package skew (1) xq7vx690t rf1157 239 ps rf1158 217 ps rf1761 284 ps rf1930 287 ps xq7vx980t rf1930 287 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest delay to longest delay from die pad to ball. 2. package delay information is available for these device/package combinations. this information can be used to deskew the pack age. table 52: package skew (cont?d) symbol description device package value units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 54 gtx transceiver specifications gtx transceiver dc input and output levels table 53 summarizes the dc specifications of the gtx tran sceivers in virtex-7 t and xt fpgas. consult the 7series fpgas gtx/gth transceiver user guide ( ug476 ) for further details. note: in figure 4 , differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2. table 53: gtx transceiver dc specifications symbol dc parameter conditions min typ max units dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting 1000 ? ? mv v cmoutdc dc common mode output voltage. equation based v mgtavtt ?dv ppout /4 mv r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? 2 12 ps dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s 150 ? 1250 mv 6.6 gb/s to 10.3125 gb/s 150 ? 1250 mv 6.6 gb/s 150 ? 2000 mv v in single-ended input voltage (2) dc coupled v mgtavtt =1.2v ?200 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt =1.2v ? 2/3 v mgtavtt ?mv r in differential input resistance ? 100 ? c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in the 7 series fpgas gtx/gth transceiver user guide ( ug476 ), and can result in values lower than reported in this table. 2. voltage measured at the pin referenced to ground. 3. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 3 figure 3: single-ended peak -to-peak voltage x-ref target - figure 4 figure 4: differential peak-to-peak voltage 0 +v p n d s 1 83 _01_062414 s ingle-ended pe a k-to-pe a k volt a ge 0 +v ?v p?n d s 1 83 _02_062414 differenti a l pe a k-to-pe a k volt a ge s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 55 table 54 summarizes the dc specifications of the cl ock input of the gtx transceiver. consult the 7 series fpgas gtx/gth transceiver user guide ( ug476 ) for further details. gtx transceiver switching characteristics consult the 7 series fpgas gtx/gth transceiver user guide ( ug476 ) for further information. table 54: gtx transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 100 ? nf table 55: gtx transceiver performance symbol description output divider speed grade units -3/-2g -2/-2l -1/-1m (1) f gtxmax (2) maximum gtx transceiver data rate 12.5 10.3125 8.0 gb/s f gtxmin (2) minimum gtx transceiver data rate 0.500 0.500 0.500 gb/s f gtxcrange cpll line rate range 1 3.2?6.6 gb/s 2 1.6?3.3 gb/s 40.8?1.65gb/s 8 0.5?0.825 gb/s 16 n/a gb/s f gtxqrange1 qpll line rate range 1 1 5.93?8.0 5.93?8.0 5.93?8.0 gb/s 2 2.965?4.0 2.965?4.0 2.965?4.0 gb/s 4 1.4825?2.0 1.4825?2.0 1.4825?2.0 gb/s 8 0.74125?1.0 0.74125?1.0 0.74125?1.0 gb/s 16 n/a n/a n/a gb/s f gtxqrange2 qpll line rate range 2 (3) 1 9.8?12.5 9.8?10.3125 n/a gb/s 2 4.9?6.25 4.9?5.15625 n/a gb/s 4 2.45?3.125 2.45?2.578125 n/a gb/s 8 1.225?1.5625 1.225?1.2890625 n/a gb/s 16 0.6125?0.78125 0.6125?0.64453125 n/a gb/s f gcpllrange gtx transceiver cpll frequency range 1.6?3.3 1.6?3.3 1.6?3.3 ghz f gqpllrange1 gtx transceiver qpll frequency ra nge 1 5.93?8.0 5.93?8.0 5.93?8.0 ghz f gqpllrange2 gtx transceiver qpll frequency range 2 9.8?12.5 9.8?10.3125 n/a ghz notes: 1. the -1 speed grade requires a 4-byte internal data wi dth for operation above 5.0 gb/s. a -1 speed grade with v ccint = 0.9v, as described in the lowering power using the voltage identification bit application note ( xapp555 ), requires a 4-byte internal data width for operation above 3.8 gb/s. 2. data rates between 8.0 gb/s and 9.8 gb/s are not available. 3. for qpll line rate range 2, the maximum line rate with the divider n set to 66 is 10.3125gb/s. table 56: gtx transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3/-2g -2/-2l -1/-1m f gtxdrpclk gtxdrpclk maximum frequency 175.01 175.01 156.25 mhz s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 56 table 57: gtx transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range -3 speed grade 60 ? 700 mhz all other speed grades 60 ? 670 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle tr ansceiver pll only 40 50 60 % x-ref target - figure 5 figure 5: reference clock timing parameters table 58: gtx transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 37 x10 6 ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ? 50,000 2.3 x10 6 ui d s 1 83 _0 3 _021611 8 0 % 20 % t fclk t rclk s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 57 table 59: gtx transceiver user clock switching characteristics (1)(2) symbol description data width conditions speed grade units internal logic interconnect logic -3/-2g (3) -2/-2l (3) -1/-1m (4) f txout txoutclk maximum frequency 412.500 412.500 312.500 mhz f rxout rxoutclk maximum frequency 412.500 412.500 312.500 mhz f txin txusrclk maximum frequency 16-bit 16-bit and 32-bit 412.500 412.500 312.500 mhz 32-bit 32-bit 390.625 322.266 250.000 mhz f rxin rxusrclk maximum frequency 16-bit 16-bit and 32-bit 412.500 412.500 312.500 mhz 32-bit 32-bit 390.625 322.266 250.000 mhz f txin2 txusrclk2 maximum frequency 16-bit 16-bit 412.500 412.500 312.500 mhz 16-bit and 32-bit 32-bit 390.625 322.266 250.000 mhz 32-bit 64-bit 195.313 161.133 125.000 mhz f rxin2 rxusrclk2 maximum frequency 16-bit 16-bit 412.500 412.500 312.500 mhz 16-bit and 32-bit 32-bit 390.625 322.266 250.000 mhz 32-bit 64-bit 195.313 161.133 125.000 mhz notes: 1. clocking must be implemented as described in the 7 series fpgas gtx/gth tr ansceiver user guide ( ug476 ). 2. these frequencies are not supported for all possible transceiver configurations. 3. for speed grades -3, -2, -2l, and -2g, a 16-bit datapath can only be used for speeds less than 6.6 gb/s. 4. for speed grade -1, a 16-bit datapath can only be used for speeds less than 5.0 gb/s. for speed grade -1c with v ccint = 0.9v, as described in the lowering power using the voltage identification bit application note ( xapp555 ), a 16-bit datapath can only be used for speeds less than 3.8 gb/s. table 60: gtx transceiver transmitter switching characteristics symbol description cond ition min typ max units f gtxtx serial data rate range 0.500 ? f gtxmax gb/s t rtx tx rise time 20%?80% ? 40 ? ps t ftx tx fall time 80%?20% ? 40 ? ps t llskew tx lane-to-lane skew (1) ? ? 500 ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 140 ns tj 12.5 total jitter (2)(4) 12.5 gb/s ? ? 0.28 ui dj 12.5 deterministic jitter (2)(4) ? ? 0.17 ui tj 11.18 total jitter (2)(4) 11.18 gb/s ? ? 0.28 ui dj 11.18 deterministic jitter (2)(4) ? ? 0.17 ui tj 10.3125 total jitter (2)(4) 10.3125 gb/s ? ? 0.28 ui dj 10.3125 deterministic jitter (2)(4) ? ? 0.17 ui tj 9.953 total jitter (2)(4) 9.953 gb/s ? ? 0.28 ui dj 9.953 deterministic jitter (2)(4) ? ? 0.17 ui tj 9.8 total jitter (2)(4) 9.8 gb/s ? ? 0.28 ui dj 9.8 deterministic jitter (2)(4) ? ? 0.17 ui tj 8.0 total jitter (2)(4) 8.0 gb/s ? ? 0.30 ui dj 8.0 deterministic jitter (2)(4) ? ? 0.15 ui tj 6.6_qpll total jitter (2)(4) 6.6 gb/s ? ? 0.28 ui dj 6.6_qpll deterministic jitter (2)(4) ? ? 0.17 ui s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 58 tj 6.6_cpll total jitter (3)(4) 6.6 gb/s ? ? 0.30 ui dj 6.6_cpll deterministic jitter (3)(4) ? ? 0.15 ui tj 5.0 total jitter (3)(4) 5.0 gb/s ? ? 0.30 ui dj 5.0 deterministic jitter (3)(4) ? ? 0.15 ui tj 4.25 total jitter (3)(4) 4.25 gb/s ? ? 0.30 ui dj 4.25 deterministic jitter (3)(4) ? ? 0.15 ui tj 3.75 total jitter (3)(4) 3.75 gb/s ? ? 0.30 ui dj 3.75 deterministic jitter (3)(4) ? ? 0.15 ui tj 3.20 total jitter (3)(4) 3.20 gb/s (5) ? ? 0.20 ui dj 3.20 deterministic jitter (3)(4) ? ? 0.10 ui tj 3.20l total jitter (3)(4) 3.20 gb/s (6) ? ? 0.32 ui dj 3.20l deterministic jitter (3)(4) ? ? 0.16 ui tj 2.5 total jitter (3)(4) 2.5 gb/s (7) ? ? 0.20 ui dj 2.5 deterministic jitter (3)(4) ? ? 0.08 ui tj 1.25 total jitter (3)(4) 1.25 gb/s (8) ? ? 0.15 ui dj 1.25 deterministic jitter (3)(4) ? ? 0.06 ui tj 500 total jitter (3)(4) 500 mb/s ? ? 0.10 ui dj 500 deterministic jitter (3)(4) ? ? 0.03 ui notes: 1. using same refclk input with tx phase alignment enabled for up to 12 consecutive transmitters (three fully populated gtx quad s). 2. using qpll_fbdiv = 40, 20-bit internal data width. these values are not intended for protocol specific compliance determination s. 3. using cpll_fbdiv = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinations . 4. all jitter values are based on a bit-error ratio of 1e -12 . 5. cpll frequency at 3.2 ghz and txout_div = 2. 6. cpll frequency at 1.6 ghz and txout_div = 1. 7. cpll frequency at 2.5 ghz and txout_div = 2. 8. cpll frequency at 2.5 ghz and txout_div = 4. table 60: gtx transceiver transmitter switching characteristics (cont?d) symbol description cond ition min typ max units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 59 table 61: gtx transceiver receiver switching characteristics symbol description min typ max units f gtxrx serial data rate 0.500 ? f gtxmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 10 ? ns rx oobvdpp oob detect threshold peak-to-peak 60 ? 150 mv rx sst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 0 ppm rx rl run length (cid) ? ? 512 ui rx ppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ?1250 ? 1250 ppm bit rates > 6.6 gb/s and 8.0 gb/s ?700 ? 700 ppm bit rates > 8.0 gb/s ?200 ? 200 ppm sj jitter tolerance (2) jt_sj 12.5 sinusoidal jitter (qpll) (3) 12.5 gb/s 0.3 ? ? ui jt_sj 11.18 sinusoidal jitter (qpll) (3) 11.18 gb/s 0.3 ? ? ui jt_sj 10.32 sinusoidal jitter (qpll) (3) 10.32 gb/s 0.3 ? ? ui jt_sj 9.95 sinusoidal jitter (qpll) (3) 9.95 gb/s 0.3 ? ? ui jt_sj 9.8 sinusoidal jitter (qpll) (3) 9.8 gb/s 0.3 ? ? ui jt_sj 8.0 sinusoidal jitter (qpll) (3) 8.0 gb/s 0.44 ? ? ui jt_sj 6.6_qpll sinusoidal jitter (qpll) (3) 6.6 gb/s 0.48 ? ? ui jt_sj 6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s 0.44 ? ? ui jt_sj 5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s 0.44 ? ? ui jt_sj 4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s 0.44 ? ? ui jt_sj 3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.2 sinusoidal jitter (cpll) (3) 3.2 gb/s (4) 0.45 ? ? ui jt_sj 3.2l sinusoidal jitter (cpll) (3) 3.2 gb/s (5) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (6) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (7) 0.5 ? ? ui jt_sj 500 sinusoidal jitter (cpll) (3) 500 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.2 total jitter with stressed eye (8) 3.2 gb/s 0.70 ? ? ui jt_tjse 6.6 6.6 gb/s 0.70 ? ? ui jt_sjse 3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s 0.1 ? ? ui jt_sjse 6.6 6.6 gb/s 0.1 ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. cpll frequency at 3.2 ghz and rxout_div = 2. 5. cpll frequency at 1.6 ghz and rxout_div = 1. 6. cpll frequency at 2.5 ghz and rxout_div = 2. 7. cpll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter with rx in lpm or dfe mode. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 60 gtx transceiver protocol jitter characteristics for table 62 through table 67 , the 7 series fpgas gtx/gth tr ansceiver user guide ( ug476 ) contains recommended settings for optimal usage of protocol specific characteristics. table 62: gigabit ethernet protocol characteristics (gtx transceivers) description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 63: xaui protocol characteristics (gtx transceivers) description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high freq uency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 64: pci express protocol characteristics (gtx transceivers) (1) standard description line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? 0.25 ui pci express gen 2 total transmitter jitter 5000 ? 0.25 ui pci express gen 3 total transmitter ji tter uncorrelated 8000 ? 31.25 ps deterministic transmitter jitter uncorrelated ? 12 ps pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 0.65 ? ui pci express gen 2 (2) receiver inherent timing error 5000 0.40 ? ui receiver inherent deterministic timing error 0.30 ? ui pci express gen 3 receiver sinusoidal jitter tolerance 0.03 mhz?1.0 mhz 8000 1.00 ? ui 1.0 mhz?10 mhz note 3 ?ui 10 mhz?100 mhz 0.10 ? ui notes: 1. tested per card electromechanical (cem) methodology. 2. using common refclk. 3. between 1 mhz and 10 mhz the minimum sinusoidal jitter roll-off with a slope of 20db/decade. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 61 table 65: cei-6g and cei-11g protocol characteristics (gtx transceivers) description line rate (mb/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g-lr ? 0.3 ui cei-6g receiver high fr equency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui cei-6g-lr 0.95 ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? 0.3 ui cei-11g-lr/mr ? 0.3 ui cei-11g receiver high fr equency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr 0.65 ? ui cei-11g-mr 0.65 ? ui cei-11g-lr 0.825 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. table 66: sfp+ protocol characteristics (gtx transceivers) description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?0.28ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) 0.7 ? ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 62 table 67: cpri protocol characteristics (gtx transceivers) description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui 9830.4 ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 0.95 ? ui 6144.0 0.95 ? ui 9830.4 note 1 ?ui notes: 1. tested per sfp+ specification, see table 66 . s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 63 gth transceiver specifications gth transceiver dc input and output levels table 68 summarizes the dc specifications of the gth tran sceivers in virtex-7 t and xt fpgas. consult the 7series fpgas gtx/gth transceiver user guide ( ug476 ) for further details. table 68: gth transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s 150 ? 1250 mv 6.6 gb/s to 10.3125 gb/s 150 ? 1250 mv 6.6 gb/s 150 ? 2000 mv v in single-ended input voltage (1) dc coupled v mgtavtt =1.2v ?400 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt =1.2v ? 2/3 v mgtavtt ?mv dv ppout differential peak-t o-peak output voltage (2) transmitter output swing is set to 1010 800 ? ? mv v cmoutdc common mode output voltage: dc coupled equation based v mgtavtt ?dv ppout /4 mv v cmoutac common mode output voltage: ac coupled equation based v mgtavtt ?dv ppout /2 mv r in differential input resistance ? 100 ? r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? ? 10 ps c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. voltage measured at the pin referenced to ground. 2. the output swing and preemphasis levels are programmable using the attributes discussed in the 7 series fpgas gtx/gth transceiver user guide ( ug476 ), and can result in values lower than reported in this table. 3. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 6 figure 6: single-ended peak -to-peak voltage 0 +v p n d s 1 83 _01_062414 s ingle-ended pe a k-to-pe a k volt a ge s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 64 note: in figure 7 , differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2. table 69 summarizes the dc specifications of the clock input of the gth transceiver. consult the 7 series fpgas gtx/gth transceiver user guide ( ug476 ) for further details. gth transceiver switching characteristics consult the 7 series fpgas gtx/gth transceiver user guide ( ug476 ) for further information. x-ref target - figure 7 figure 7: differential peak-to-peak voltage table 69: gth transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 350 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 100 ? nf table 70: gth transceiver performance symbol description output divider speed grade units -3e/-2ge -2(c/i)/-2le -1(c/i/m) (1) f gthmax maximum gth transceiver data rate 13.1 11.3 8.5 gb/s f gthmin minimum gth transceiver data rate 0.500 0.500 0.500 gb/s f gthcrange cpll line rate range 1 3.2?10.3125 3.2?8.0 gb/s 2 1.6?5.16 1.6?4.0 gb/s 4 0.8?2.58 0.8?2.0 gb/s 8 0.5?1.29 0.5?1.0 gb/s 16 n/a gb/s f gthqrange1 qpll line rate range 1 1 8.0?11.85 8.0?11.3 8.0?8.5 gb/s 2 4.0?5.925 4.0?5.925 4.0?4.25 gb/s 4 2.0?2.9625 2.0?2.9625 2.0?2.125 gb/s 8 1.0?1.48125 1.0?1.48125 1.0?1.0625 gb/s 16 0.5?0.740625 0.5?0.740625 0.5?0.53125 gb/s f gthqrange2 qpll line rate range 2 1 11.85?13.1 n/a gb/s 2 5.925?6.55 5.925?6.25 n/a gb/s 4 2.9625?3.275 2.9625?3.125 n/a gb/s 8 1.48125?1.63 1.48125?1.5625 n/a gb/s 16 0.740625?0.81875 0. 740625?0.78125 n/a gb/s f gcpllrange gth transceiver cpll frequen cy range 1.6?5.16 1.6?4.0 ghz 0 +v ?v p?n d s 1 83 _02_062414 differenti a l pe a k-to-pe a k volt a ge s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 65 f gqpllrange1 gth transceiver qpll frequency ra nge 1 8.0?11.85 8.0?11.85 8.0?8.5 ghz f gqpllrange2 gth transceiver qpll frequency range 2 11.85?13.1 11.85?12.5 n/a ghz notes: 1. the -1 speed grade requires a 4-byte internal data width for operation above 5.0 gb/s. a -1 speed grade with v ccint = 0.9v, as described in the lowering power using the voltage identification bit application note ( xapp555 ), requires a 4-byte internal data width for operation above 3.8 gb/s. table 71: gth transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3/-2g -2l -2 -1/-1m f gthdrpclk gthdrpclk maximum frequency 1 75.01 175.01 175.01 156.25 mhz table 72: gth transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range 60 ? 820 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle tr ansceiver pll only 40 50 60 % x-ref target - figure 8 figure 8: reference clock timing parameters table 73: gth transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 37 x10 6 ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ? 50,000 2.3 x10 6 ui table 70: gth transceiver performance (cont?d) symbol description output divider speed grade units -3e/-2ge -2(c/i)/-2le -1(c/i/m) (1) d s 1 83 _0 3 _021611 8 0 % 20 % t fclk t rclk s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 66 table 74: gth transceiver user clock switching characteristics (1) symbol description data width conditions speed grade units internal logic interconnect logic -3e/-2ge (2) -2(c/i)/-2le (2) -1(c/i/m) (3) f txout txoutclk maximum frequency 412.500 412.500 312.500 mhz f rxout rxoutclk maximum frequency 412.500 412.500 312.500 mhz f txin txusrclk maximum frequency 16-bit 16-bit and 32-bit 412.500 412.500 312.500 mhz 32-bit 32-bit 409.375 353.125 265.625 mhz f rxin rxusrclk maximum frequency 16-bit 16-bit and 32-bit 412.500 412.500 312.500 mhz 32-bit 32-bit 409.375 353.125 265.625 mhz f txin2 txusrclk2 maximum frequency 16-bit 16-bit 412.500 412.500 312.500 mhz 16-bit and 32-bit 32-bit 409.375 353.125 265.625 mhz 32-bit 64-bit 204.688 176.563 132.813 mhz f rxin2 rxusrclk2 maximum frequency 16-bit 16-bit 412.500 412.500 312.500 mhz 16-bit and 32-bit 32-bit 409.375 353.125 265.625 mhz 32-bit 64-bit 204.688 176.563 132.813 mhz notes: 1. clocking must be implemented as described in the 7 series fpgas gtx/gth tr ansceiver user guide ( ug476 ). 2. for speed grades -3e, -2ge, -2c, -2i, and -2le, a 16-bit datapath can only be used for line rates less than 6.6 gb/s. 3. for speed grade -1 with v ccint = 0.9v, as described in the lowering power using the voltage identification bit application note ( xapp555 ), a 16-bit datapath can only be used for line rates less than 3.8 gb/s. for speed grade -1 with v ccint = 1.0v, a 16-bit datapath can only be used for line rates less than 5.0 gb/s. table 75: gth transceiver transmitter switching characteristics symbol description cond ition min typ max units f gthtx serial data rate range 0.500 ? f gthmax gb/s t rtx tx rise time 20%?80% ? 40 ? ps t ftx tx fall time 80%?20% ? 40 ? ps t llskew tx lane-to-lane skew (1) ? ? 500 ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 140 ns tj 13.1 total jitter (2)(4) 13.1 gb/s ??0.3ui dj 13.1 deterministic jitter (2)(4) ? ? 0.17 ui tj 12.5 total jitter (2)(4) 12.5 gb/s ? ? 0.28 ui dj 12.5 deterministic jitter (2)(4) ? ? 0.17 ui tj 11.3 total jitter (2)(4) 11.3 gb/s ? ? 0.28 ui dj 11.3 deterministic jitter (2)(4) ? ? 0.17 ui tj 10.3125_qpll total jitter (2)(4) 10.3125 gb/s ? ? 0.28 ui dj 10.3125_qpll deterministic jitter (2)(4) ? ? 0.17 ui tj 10.3125_cpll total jitter (3)(4) 10.3125 gb/s ? ? 0.33 ui dj 10.3125_cpll deterministic jitter (3)(4) ? ? 0.17 ui tj 9.953 total jitter (2)(4) 9.953 gb/s ? ? 0.28 ui dj 9.953 deterministic jitter (2)(4) ? ? 0.17 ui tj 9.8 total jitter (2)(4) 9.8 gb/s ? ? 0.28 ui dj 9.8 deterministic jitter (2)(4) ? ? 0.17 ui s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 67 tj 8.0_qpll total jitter (2)(4) 8.0 gb/s ? ? 0.28 ui dj 8.0_qpll deterministic jitter (2)(4) ? ? 0.17 ui tj 8.0_cpll total jitter (3)(4) 8.0 gb/s ? ? 0.32 ui dj 8.0_cpll deterministic jitter (3)(4) ? ? 0.17 ui tj 6.6_cpll total jitter (3)(4) 6.6 gb/s ? ? 0.30 ui dj 6.6_cpll deterministic jitter (3)(4) ? ? 0.15 ui tj 5.0 total jitter (3)(4) 5.0 gb/s ? ? 0.30 ui dj 5.0 deterministic jitter (3)(4) ? ? 0.15 ui tj 4.25 total jitter (3)(4) 4.25 gb/s ? ? 0.30 ui dj 4.25 deterministic jitter (3)(4) ? ? 0.15 ui tj 3.75 total jitter (3)(4) 3.75 gb/s ? ? 0.30 ui dj 3.75 deterministic jitter (3)(4) ? ? 0.15 ui tj 3.20 total jitter (3)(4) 3.20 gb/s (5) ??0.2ui dj 3.20 deterministic jitter (3)(4) ??0.1ui tj 3.20l total jitter (3)(4) 3.20 gb/s (6) ? ? 0.32 ui dj 3.20l deterministic jitter (3)(4) ? ? 0.16 ui tj 2.5 total jitter (3)(4) 2.5 gb/s (7) ? ? 0.20 ui dj 2.5 deterministic jitter (3)(4) ? ? 0.08 ui tj 1.25 total jitter (3)(4) 1.25 gb/s (8) ? ? 0.15 ui dj 1.25 deterministic jitter (3)(4) ? ? 0.06 ui tj 500 total jitter (3)(4) 500 mb/s ??0.1ui dj 500 deterministic jitter (3)(4) ? ? 0.03 ui notes: 1. using same refclk input with tx phase alignment enabled for up to 12 consecutive transmitters (three fully populated gth quad s). 2. using qpll_fbdiv = 40, 20-bit internal data width. these values are not intended for protocol specific compliance determination s. 3. using cpll_fbdiv = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinations . 4. all jitter values are based on a bit-error ratio of 1e -12 . 5. cpll frequency at 3.2 ghz and txout_div = 2. 6. cpll frequency at 1.6 ghz and txout_div = 1. 7. cpll frequency at 2.5 ghz and txout_div = 2. 8. cpll frequency at 2.5 ghz and txout_div = 4. table 75: gth transceiver transmitter switching characteristics (cont?d) symbol description cond ition min typ max units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 68 table 76: gth transceiver receiver switching characteristics symbol description min typ max units f gthrx serial data rate 0.500 ? f gthmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 10 ? ns rx oobvdpp oob detect threshold peak-to-peak 60 ? 150 mv rx sst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 0 ppm rx rl run length (cid) ? ? 512 ui rx ppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ?1250 ? 1250 ppm bit rates > 6.6 gb/s and 8.0 gb/s ?700 ? 700 ppm bit rates > 8.0 gb/s ?200 ? 200 ppm sj jitter tolerance (2) jt_sj 13.1 sinusoidal jitter (qpll) (3) 13.1 gb/s 0.3 ? ? ui jt_sj 12.5 sinusoidal jitter (qpll) (3) 12.5 gb/s 0.3 ? ? ui jt_sj 11.3 sinusoidal jitter (qpll) (3) 11.3 gb/s 0.3 ? ? ui jt_sj 10.32_qpll sinusoidal jitter (qpll) (3) 10.32 gb/s 0.3 ? ? ui jt_sj 10.32_cpll sinusoidal jitter (cpll) (3) 10.32 gb/s 0.3 ? ? ui jt_sj 9.8 sinusoidal jitter (qpll) (3) 9.8 gb/s 0.3 ? ? ui jt_sj 8.0_qpll sinusoidal jitter (qpll) (3) 8.0 gb/s 0.44 ? ? ui jt_sj 8.0_cpll sinusoidal jitter (cpll) (3) 8.0 gb/s 0.42 ? ? ui jt_sj 6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s 0.44 ? ? ui jt_sj 5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s 0.44 ? ? ui jt_sj 4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s 0.44 ? ? ui jt_sj 3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.2 sinusoidal jitter (cpll) (3) 3.2 gb/s (4) 0.45 ? ? ui jt_sj 3.2l sinusoidal jitter (cpll) (3) 3.2 gb/s (5) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (6) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (7) 0.5 ? ? ui jt_sj 500 sinusoidal jitter (cpll) (3) 500 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.2 total jitter with stressed eye (8) 3.2 gb/s 0.70 ? ? ui jt_tjse 6.6 6.6 gb/s 0.70 ? ? ui jt_sjse 3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s 0.1 ? ? ui jt_sjse 6.6 6.6 gb/s 0.1 ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. cpll frequency at 3.2 ghz and rxout_div = 2. 5. cpll frequency at 1.6 ghz and rxout_div = 1. 6. cpll frequency at 2.5 ghz and rxout_div = 2. 7. cpll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter with rx in lpm or dfe mode. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 69 gth transceiver protocol jitter characteristics for table 77 through table 82 , the 7 series fpgas gtx/gth tr ansceiver user guide ( ug476 )contains recommended settings for optimal usage of protocol specific characteristics. table 77: gigabit ethernet protocol characteristics (gth transceivers) description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 78: xaui protocol characteristics (gth transceivers) description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high freq uency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 79: pci express protocol characteristics (gth transceivers) (1) standard description line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? 0.25 ui pci express gen 2 total transmitter jitter 5000 ? 0.25 ui pci express gen 3 total transmitter ji tter uncorrelated 8000 ? 31.25 ps deterministic transmitter jitter uncorrelated ? 12 ps pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 0.65 ? ui pci express gen 2 receiver inherent timing error 5000 0.40 ? ui receiver inherent deterministic timing error 0.30 ? ui pci express gen 3 receiver sinusoidal jitter tolerance 0.03 mhz?1.0 mhz 8000 1.00 ? ui 1.0 mhz?10 mhz note 3 ?ui 10 mhz?100 mhz 0.10 ? ui notes: 1. tested per card electromechanical (cem) methodology. 2. using common refclk. 3. between 1 mhz and 10 mhz the minimum sinusoidal jitter roll-off with a slope of 20db/decade. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 70 table 80: cei-6g and cei-11g protocol characteristics (gth transceivers) description line rate (mb/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g-lr ? 0.3 ui cei-6g receiver high fr equency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui cei-6g-lr 0.95 ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? 0.3 ui cei-11g-lr/mr ? 0.3 ui cei-11g receiver high fr equency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr 0.65 ? ui cei-11g-mr 0.65 ? ui cei-11g-lr 0.825 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. table 81: sfp+ protocol characteristics (gth transceivers) description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?0.28ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) 0.7 ? ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 71 integrated interface bloc k for pci express designs switching characteristics more information and documentation on solutions for pci express designs can be found at: http://www.xilinx.com /technology/protoco ls/pciexpress.htm table 82: cpri protocol characteristics (gth transceivers) description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui 9830.4 ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 0.95 ? ui 6144.0 0.95 ? ui 9830.4 note 1 ?ui notes: 1. tested per sfp+ specification, see table 81 . table 83: maximum performance for pci express designs symbol description speed grade units -3 -2/-2l/-2g -1/1m f pipeclk pipe clock maximum frequency 250.00 250.00 250.00 mhz f userclk user clock maximum frequency 500.00 (1) 500.00 (1) 250.00 mhz f userclk2 user clock 2 maximum frequency 250.00 250.00 250.00 mhz f drpclk drp clock maximum frequency 250.00 250.00 250.00 mhz notes: 1. pci express x8 gen 2 operation is only supported in -2 and -3 speed grades for devices that have gtx transceivers. refer to 7series fpgas integrated block for pci express product guide ( pg054 ) for specific supported core configurations. 2. pci express gen 3 operation is only supported in -2 and -3 speed grades for devices that have gth transceivers. refer to virtex-7 fpga gen3 integrated block for pci express v3.0 ( pg023 ) for specific supported core configurations. s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 72 xadc specifications table 84: xadc specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 5%, v refp = 1.25v, v refn = 0v, adcclk = 26 mhz, t j = ?40c to 100c, typical values at t j =+40c adc accuracy (1) resolution 12 ? ? bits integral nonlinearity (2) inl ? ? 3 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ? ? 1 lsbs offset error offset calibration enabled ? ? 6 lsbs gain error gain calibration disabled ? ? 0.5 % offset matching offset calibration enabled ? ? 4 lsbs gain matching gain calibration disabled ? ? 0.3 % sample rate ?? 1 ms/s signal to noise ratio (2) snr f sample = 500ks/s, f in =20khz 60 ? ? db rms code noise external 1.25v reference ? ? 2 lsbs on-chip reference ? 3 ? lsbs total harmonic distortion (2) thd f sample = 500ks/s, f in =20khz ? 70 ? db adc accuracy at extended temperatures resolution t j = ?55c to 125c 10 ? ? bits integral nonlinearity (2) inl t j = ?55c to 125c ? ? 1 lsb (at 10 bits) differential nonlinearity dnl no mi ssing codes, guaranteed monotonic, t j = ?55c to 125c ??1 analog inputs (3) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v auxiliary channel full resolution bandwidth frbw 250 ? ? khz on-chip sensors temperature sensor error t j = ?40c to 100c. ? ? 4 c t j = ?55c to +125c ? ? 6 c supply sensor error measurement range of v ccaux 1.8v 5% t j = ?40c to +100c ??1 % measurement range of v ccaux 1.8v 5% t j = ?55c to +125c ??2 % conversion rate (4) conversion time - continuous t conv number of adcclk cycles 26 ? 32 cycles conversion time - event t conv number of clk cycles ? ? 21 cycles drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 26 mhz s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 73 configuration switching characteristics dclk duty cycle 40 ? 60 % xadc reference (5) external reference v refp externally supplied reference voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, t j = ?40c to 100c 1.2375 1.25 1.2625 v notes: 1. offset and gain errors are removed by enabling the xadc automatic gain calibration feature. the values are specified for when this feature is enabled. 2. only specified for the bitstream option xadcenhancedlinearity = on. 3. for a detailed description, see the adc chapter in the 7 series fpgas and zynq-7000 ap soc xadc dual 12-bit 1 msps analog-to-digital converter ( ug480 ). 4. for a detailed description, see the timing chapter in the 7 series fpgas and zynq-7000 ap soc xa dc dual 12-bit 1 msps analog-to- digital converter ( ug480 ). 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. on-chip reference variation is 1%. table 85: configuration switching characteristics symbol description virtex-7 t and xt devices speed grade units -3 -2/-2l/-2g -1/-1m power-up timing characteristics t pl (1) program latency 5 5 5 ms, max t por (1) power-on reset (50ms ramp rate time) 10/50 10/50 1 0/50 ms, min/max power-on reset (1ms ramp rate time) 10/35 10/35 1 0/35 ms, min/max t program program pulse width 250 250 250 ns, min cclk output (master mode) t icck master cclk output delay 150 150 150 ns, min t mcckl master cclk clock low time duty cycle 40/60 40/60 40/60 %, min/max t mcckh master cclk clock high time duty cycle 40/60 40/60 40/60 %, min/max f mcck master cclk frequency 100 100 100 mhz, max master cclk frequency for aes encrypted x16 50 50 50 mhz, max f mcck_start master cclk frequency at start of configuration 3 3 3 mhz, typ f mccktol frequency tolerance, master mode with respect to nominal cclk. 50 50 50 %, max cclk input (slave modes) t scckl slave cclk clock minimum low time 2.5 2.5 2.5 ns, min t scckh slave cclk clock minimum high time 2.5 2.5 2.5 ns, min f scck slave cclk frequency 100 100 100 mhz, max emcclk input (master mode) t emcckl external master cclk low time 2.5 2.5 2.5 ns, min t emcckh external master cclk hi gh time 2.5 2.5 2.5 ns, min f emcck external master cclk frequency 100 100 100 mhz, max table 84: xadc specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 74 internal configuration access port f icapck internal configuration access port (icape2) master slr icap accessing the entire device 70.00 70.00 70.00 mhz, max slr icap accessing the local slr 100.00 100.00 100.00 mhz, max all other devices 100.00 100.00 100.00 mhz, max master/slave serial mode programming switching t dcck /t cckd din setup/hold 4.0/0.0 4.0/0.0 4.0/0.0 ns, min t cco dout clock to out 8.0 8.0 8.0 ns, max selectmap mode programming switching t smdcck /t smcckd d[31:00] setup/hold 4.0/0 .0 4.0/0.0 4.0/0.0 ns, min t smcscck /t smcckcs csi_b setup/hold 4.0/0.0 4.0/0.0 4.0/0.0 ns, min t smwcck /t smcckw rdwr_b setup/hold 10.0/0.0 10.0/0.0 10.0/0.0 ns, min t smckcso cso_b clock to out (330 pull-up resistor required) 7.0 7.0 7.0 ns, max t smco d[31:00] clock to out in readback 8.0 8.0 8.0 ns, max f rbcck readback frequency slr-based n/a 70 70 mhz, max all other devices 100 100 100 mhz, max boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup/hold slr-based n/a 9.0/2.0 9.0/2.0 ns, min all other devices 3.0/2.0 3.0/2.0 3.0/2.0 ns, min t tcktdo tck falling edge to tdo output slr-based n/a 17 17 ns, max all other devices 7.0 7.0 7.0 ns, max f tck tck frequency slr-based n/a 20 20 mhz, max all other devices 66 66 66 mhz, max bpi flash master mode programming switching t bpicco (2) a[28:00], rs[1:0], fcs_b, foe_b, fwe_b, adv_b clock to out 8.5 8.5 8.5 ns, max t bpidcc /t bpiccd d[15:00] setup/hold 4.0/0 .0 4.0/0.0 4.0/0.0 ns, min spi flash master mode programming switching t spidcc /t spiccd d[03:00] setup/hold 3.0/0 .0 3.0/0.0 3.0/0.0 ns, min t spiccm mosi clock to out 8.0 8.0 8.0 ns, max t spiccfc fcs_b clock to out 8.0 8.0 8.0 ns, max startupe2 ports t usrcclko startupe2 usrcclko input to cclk output 0. 50/6.00 0.50/6.70 0.50/7.50 ns, min/max f cfgmclk startupe2 cfgmclk output frequency 65.00 65.00 65.00 mhz, typ f cfgmclktol startupe2 cfgmclk output frequency tolerance 50 50 50 %, max device dna access port f dnack dna access port (dna_port) 100.00 100.00 100.00 mhz, max notes: 1. to support longer delays in configuration, use the design solutions described in the 7 series fpga configuration user guide ( ug470 ). 2. only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the i/o. table 85: configuration switching characteristics (cont?d) symbol description virtex-7 t and xt devices speed grade units -3 -2/-2l/-2g -1/-1m s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 75 efuse programming conditions table 86 lists the programming conditions specifically for efuse. for more information, see the 7 series fpga configuration user guide ( ug470 ). revision history the following table shows the revision history for this document. table 86: efuse programming conditions (1) symbol description min typ max units i fs v ccaux supply current ? ? 115 ma t j temperature range 15 ? 125 c notes: 1. the fpga must not be configured during efuse programming. date version description 03/01/2011 1.0 initial xilinx release. 10/05/2011 1.1 removed the xc7v285t, xc7v450t, and xc7v 855t devices from the entir e data sheet. added the xc7vx330t, xc7vx415t, xc7vx550t, xc7vx690t, XC7VX980T, and xc7vx1140t devices to the entire data sheet. replaced -1l with -2l throughout this data sheet. added the extended temperature range discussion to page 1 . updated min/max values and removed note 5 from table 2 . clarified power-on/off power supply sequencing power sequencing discussion including adding t vcco2vccaux to table 8 . added i ccaux_io and i ccbram to table 6 and table 7 . updated v icm in table 12 and table 13 . added note 1 to table 12. updated table 86 including adding note 1 . added table 13. revised the reference clock maximum frequency (f gclk ) in table 57 . added table 59 . added gth transceiver specifications section. removed erroneous instances of hstl_iii from table 20 . removed the i/o standard adjustment measurement methodology section. use ibis for mo re accurate information and measurements. updated t idelaypat_jit in table 28 . added t as /t ah to table 30 . added t rdck_di_wf_nc /t rckd_di_wf_nc and t rdck_di_rf /t rckd_di_rf to table 33 . completely updated the specifications in table 85 . updated mmcm_f induty and added f injitter , t outjitter , and t extfdvar and note 3 to table 40 . updated the ac switching characteristics section. updated the table 52 package list. updated the notice of disclaimer . 11/07/2011 1.2 added -2g speed grade, wh ere appropriate, throughout document. revised the v ocm specification in table 12 . updated the ac switching characteristics based upon the ise 13.3 v1.02 speed specificat ion throughout document including table 19 and table 20 . added mmcm to the symbol names of a few specifications in table 40 and pll to the symbol names in table 41 . in table 42 through table 49 , updated the pin-to-pin descrip tion with the sstl15 standard. updated units in table 51 . 02/13/2012 1.3 updated summary description on page 1 . in table 2 , revised v cco for the 3.3v hr i/o banks and updated t j . added typical numbers to table 3 . updated the notes in table 6 . added mgtavcc, mgtavtt, and mgtvccaux power supply ramp times to table 8 . rearranged table 9 , added mobile_ddr, hstl_i_18, hs tl_ii_18, hsul_12, sstl135_r , sstl15_r, and sstl12 and removed diff_sstl135, diff_ sstl18_i, diff_sstl18_ii, diff _hstl_i, and diff_hstl_ii. added table 10 and table 11 . revised the specifications in table 12 and table 13 . updated the efuse programming conditions section and removed the endurance table. added the io_fifo switching characteristics table. revised i ccadc and updated note 1 in table 84 . revised ddr lvds transmitter data width in table 17 . updated the ac switching characteristics based upon the ise 13.4 v1.03 speed specification throughout document. removed notes from table 30 as they are no longer applicable. updated specifications in table 85 . updated note 1 in table 39 . in the gtx transceiver specifications section: revised v in , and added i dcin and i dcout to table 53 . updated and added notes to table 55 . in table 57 , revised f gclk , removed t phase , and added t dlock . revised specifications and added note 2 to table 59 . added table 60 and table 61 along with gtx transceiver protocol jitter characteristics in table 62 through table 67 . s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 76 05/23/2012 1.4 reorganized entire data sheet including adding table 46 and table 50 . updated t sol in table 1 . updated i batt and added r in_term to table 3 . added values to table 6 and table 7 . updated power-on/off power supply sequencing section with regards to gtx/gth transceivers. updated many parameters in table 9 , including sstl135 and sstl135_r. removed v ox column and added diff_hsul_12 to table 11 . updated v ol in table 12 . updated table 17 and removed notes 2 and 3. updated table 18 . updated the ac switching characteristics section based upon the ise 14.1 v1.04 for the -3, -2, -2l (1.0v), -1, and v1.05 for the -2l (0.9v) spe ed specifications thro ughout the document. in table 33 , updated reset delays section including note 10 and note 11 . added data for t lock and t dlock in table 57 . updated many of the xadc specifications in table 84 and added note 2 . updated and moved dynamic reconfiguration port (drp) for mmcm before and after dclk section from table 85 to table 40 and table 41 . 08/03/2012 1.5 updated the descriptions, changed v in and note 2 and added note 4 in table 1 . in table 2 , changed descriptions and notes, removed note 7, changed gtx transceiver parameters and values and added note 13 and note 14 . updated parameters in table 3 . added table 4 and table 5 . updated the values for in table 7 . updated lvcmos12 and the sstls in table 9 . updated many of the specifications in table 10 and table 11 . updated the ac switching characteristics section, based upon table 14 , for the ise 14.2 speed specifications throughout the docu ment with appropriate changes to table 15 and table 16 including production release of the xc7vx485t in the -2 and -1 speed designations. added notes and specifications to table 18 . updated the iob pad input/output/3-state discussion and changed table 21 by adding t ioibufdisable . removed many of the combinatorial delay specifications and t cinck /t ckcin from table 30 . rearranged table 53 including moving some parameters to table 1 . added table 58 . updated table 59 . in table 61 , updated sj jitter tolerance with stressed eye section, page 57 and note 8 . added note 1 , note 2 , and note 2 to table 64 . added note 1 and note 2 to table 65 , and line rate ranges. updated table 66 including adding note 1 . updated table 67 including adding note 1 . in table 84 updated note 1 and added note 4. in table 85 , updated t por and f emcck . 09/20/2012 1.6 removed the xc7v1500t device from data sheet. in table 2 , revised v ccint and v ccbram and added note 3 . updated some of the values in table 7 . revised table 15 and table 16 to include production release of the xc7v585t in the -2 and -1 speed designations. added values for the xc7v585t in table 52 . updated note 2 in table 60 . 09/26/2012 1.7 revised table 15 and table 16 to include production release of the xc7vx485t in the -3 speed designation. 10/19/2012 1.8 revised table 15 and table 16 to include production release of the xc7vx485t in the -2l (1.0v) speed designation. removed -2l (0.9v) speed specifications from data sheet, this change includes edits to v ccint and v ccbram in table 2 , editing note 1 and removing note 2 in table 55 . also in table 55 , updated the f gtxmax , f gtxqrange1 , and f gqpllrange1 specification for -1 speed grade from 6.6 gb/s to 8.0 gb/s. edited note 4 in table 59 and note 3 in table 74 . 12/12/2012 1.9 updated the ac switching characteristics section, based upon table 14 , for the ise 14.3 speed specifications throughout the document. revised table 15 and table 16 to include production release of the xc7v585t in the -3 and -2l(1.0v) speed designations. updated the notes in table 52 . updated gth transceiver specifications including removal of gth transceiver dc characteristics section (use the xpe (download at http://www.xilinx.com/power ). updated table 70 and added table 73 , table 75 , and table 76 . removed note 4 from table 84 . 12/24/2012 1.10 updated the ac switching characteristics section, based upon table 14 , for the ise 14.4 and vivado 2012.4 speed specifications throughout the document. revised the xc7v2000t in the -1 and -2 speed designations table 15 to preliminary. added the gth transceiver protocol jitter characteristics section. updated t tcktdo and added internal configuration access port section to table 85 . 01/31/2013 1.11 added note 2 to table 2 . revised table 15 and table 16 to include production release of the xc7v2000t in the -1 and -2 speed specifications. updated note 1 in table 37 . updated the notes in table 39 , table 42 through table 45 , table 48 , and table 49 . in table 68 , updated d vppin . in table 69 , updated v idiff . removed t lock and t phase from table 72 . updated t dlock in table 73 . date version description s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 77 03/07/2013 1.12 updated the ac switching characteristics section, based upon table 14 , for the ise 14.5 and vivado 2013.1 speed specifications throughout the document. revised table 15 and table 16 to include production release of the xc7vx690t. revised d vppout in table 68 . updated values in table 69 and table 76 . removed note 1 from table 70 . updated mmcm_f pfdmax in table 40 and pll_f pfdmax in table 41 . added skew values to table 52 . 03/27/2013 1.13 in table 7 , added values for the xc7vx330t and xc7vx415t devices. revised table 15 and table 16 to include production release of the xc7vx330t and xc7vx415t. in table 18 , updated the table title, lpddr2 values, and removed note 3. removed note 2: for qpll line rate, the maximum line rate with the divider n set to 66 is 10.3125 gb/s from table 70 . 04/17/2013 1.14 updated the ac switching characteristics section with production release changes to table 15 and table 16 for xc7vx550t for all speed specifications. in table 1 , revised v in (i/o input voltage) to match values in table 4 and table 5 , and combined note 4 with old note 5 and then added new note 5 . revised v in description and added note 9 in table 2 . updated first 3 rows in table 4 and table 5 . updated values and added new values to table 7 . also revised pci33_3 voltage minimum in table 10 to match values in table 1 , table 4 , and table 5 . added note 1 to table 12 and table 13 . throughout the data sheet ( table 31 , table 32 , and table 47 ) removed the obvious note ?a zero ?0? hold time listing indicates no hold time or a negative hold time.? updated and clarified usrclk data in table 59 and table 74 . 05/07/2013 1.15 revised table 15 and table 16 for the production release of the xc7v2000t and XC7VX980T devices. 05/15/2013 1.16 revised table 15 and table 16 for the production release of the xc7vx1140t devices. 09/04/2013 1.17 in table 1 , updated i dcin and i dcout section for cases wh en floating, at v mgtavtt , or gnd. removed notes from table 7 . updated f max_preadd_mult_noadreg_patdet for -1 speed grade in table 34 . in table 59 and table 74 , updated number of bits in internal logic column for f txin2 and f rxin2 from 64 to 32. updated note 8 and description of f gtxrx in table 61 . updated f gthqrange1 , f gthqrange2 , f gqpllrange1 , and f gqpllrange2 in table 70 . updated clock names and note 2 and note 3 in table 74 . removed tj 6.6_qpll and dj 6.6_qpll from table 75 . updated description of f gthrx , removed jt_sj 6.6_qpll , and updated note 8 in table 76 . replaced bitgen with bitstream in note 2 of table 84 . updated f rbcck , t taptck /t tcktap , t tcktdo , and f tck in table 85 . 11/26/2013 1.18 added virtex-7q defense-grade devices throughout. added -1m speed grade throughout. added reference to 7 series fpgas overview and defense-grade 7 series fpgas overview in introduction . in table 2 , added junction temperature operating r ange for military (m) devices and updated note 6 . in table 3 , removed commercial (c), industrial (i), and extended (e) from descriptions of r in_term . updated temperature ranges in table 4 and table 5 . added t j = 125c to conditions column for t vcco2vccaux in table 8 . updated to ise design suite 14.7 and vivado design suite 2013.3 in ac switching characteristics . added 1.05 and 1.06 rows to table 14 . added -1m speed grade to table 70 and table 74 . added t usrcclko and f dnack to table 85 . 03/04/2014 1.19 in table 2 , removed 1.0v from note 6 and added note 7 . added note 2 to table 4 . added note 2 and updated note 3 in table 5 . updated to vivado design suite 2013.4 in ac switching characteristics . revised table 15 and table 16 for the production release of the xq7vx690t devices. added hsul_12_f, diff_hsul_12_f, mobile_ddr_s, mobile_ddr_f, diff _mobile_ddr_s, and diff_mobile_ddr_f standards to and updated values in table 19 . added hsul_12_f, diff_hsul_12_f, diff_hsul_12_dci_s, and di ff_hsul_12_dci_f stan dards to and updated values in table 20 . removed notes from table 19 and table 20 . removed introductory paragraph of device pin-to-pin outp ut parameter guidelines and device pin-to-pin input parameter guidelines . enhanced precision of f gthdrpclk numbers in table 71 . added note 1 to table 83 . updated display format of ?adc accuracy at extended temperatures? section in table 84 . updated f icapck in table 85 . 04/11/2014 1.20 revised table 15 and table 16 for the production release of the xq7vx485t devices. updated note 1 in table 83 . 07/01/2014 1.21 in table 4 and table 5 , updated note 2 per the customer notice xcn14014 : 7 series fpga and zynq-7000 ap soc i/o undershoot voltage data sheet update . in power-on/off power supply sequencing , added sentence about there being no recommended sequence for supplies not shown. in table 15 , moved all xq7v585t, xq7vx330t, and xq7 vx980t speed grades from preliminary to production. in table 16 , added production software for -2, -2l, -1, and -1m speed grades of xq7v585t and xq7vx330t, and -2l and -1m sp eed grades of xq7vx980t. added note 3 to table 18 . in table 28 , added attribute refclk frequency of 400 mhz to f idelayctrl_ref and average tap delay at 400 mhz to note 1 . updated description of t ickof in table 42 and added note 2 . updated description of t ickoffar in table 43 and added note 2 . in table 52 , updated t pkgskew for xq7vx980t to 287 ps. in table 53 , moved dv ppout value of 1000 mv from max to min column, updated v in dc parameter description, and added note 2 . date version description s e n d f e e d b a c k
virtex-7 t and xt fpgas data sheet: dc and ac switching characteristics ds183 (v1.26) march 28, 2016 www.xilinx.com product specification 78 notice of disclaimer the information disclosed to you hereunder (the "materials") is prov ided solely for the selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are m ade available "as is" and with all faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or stat utory, including but not limited to warranties of merchantability, non-infringement, or fitness for any particular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includi ng your use of the materials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had been advised of the p ossibility of the same. xilinx assumes no obligation to correct any errors co ntained in the materials, or to advise you of any corrections or update. you may not reproduce, modify, distribute, or publicly display the materials wit hout prior written consent. certain products ar e subject to the terms and conditions of xilinx?s limi ted warranty, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be fail-safe or for us e in any application requiring fa il-safe performance; you assume sole risk and liability for use of xilinx products in such critical applications, please refer to xili nx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos . automotive applicat ions disclaimer xilinx products are not designed or intended to be fa il-safe, or for use in an y application requiring fail- safe performance, such as applications related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy f eature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a warning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. customer assumes the sole risk and liability of any use of xilinx products in such applications. 07/01/2014 1.21 (cont?d) added ?peak-to-peak? to labels in figure 3 and figure 4 . added note after figure 4 . in table 68 , updated v in dc parameter description, moved dv ppout value of 800 mv from max to min column, and added note 1 . added ?peak-to-peak? to labels in figure 6 and figure 7 . added note after figure 7 . in table 83 , updated note 1 and added note 2 . in table 85 , replaced usrcclk output with startupe2 ports and added f cfgmclk and f cfgmclktol . 03/06/2015 1.22 updated note 3 in table 6 . in table 12 , changed maximum v icm value from 1.425v to 1.500v. removed minimum sample rate specification from table 84 . 06/23/2015 1.23 added ffv1157, ffv1158, ffv1 761, ffv1927, and rf1158 packages to table 52 . 09/24/2015 1.24 added introdu ctory paragraph before table 18 . updated note 3 in table 18 . removed note about pci-sig 3.0 certification and compliance test boards from table 64 and table 79 . updated f icapck description from icape3 to icape2 in table 85 . 02/02/2016 1.25 added i/o standard adjustment measurement methodology . 03/28/2016 1.26 updated v meas for lvcmos33, lvttl, and pci33_3 in table 22 . date version description s e n d f e e d b a c k

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